Patent US3683202A successfully refreshed from Google Patents.
US3683202A
Expired / Lapsed
US
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Complementary metal oxide semiconductor exclusive nor gate
Assignee: Motorola Solutions Inc
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Filing: 1970-12-28
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Granted: 1972-08-08
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Expires: 1990-12-28
Abstract
Abstract A complementary metal oxide semiconductor (CMOS) exclusive NOR gate is shown having a minimum number of devices for performing the exclusive NOR function. The exclusive NOR function is performed by utilizing the normal two input signals as logic indicating signals and generating a control signal which is a complement of one of the two logic signals. A different configuration results with the selection of the logic signal from which the control signal is to be generated. The capacitance of the output node or output signal is charged by any one of a plurality of current paths associated with each logic configuration.
Inventors
- 👤 Bernard H Schmidt Jr
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 23:34
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/20; H03K19/21; H03K19/215
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
252 words
A CMOS exclusive NOR circuit comprising: a source of potential having a first voltage level and a second voltage level and said second voltage level being more negative than said first voltage level; a first input logic terminal and a second second input terminal; a first logic signal applied to said first terminal and a second logic signal applied to said second terminal; an output terminal; a first current charging and discharging path including said output terminal; a first P-channel, enhancement mode, MOSFET having source, drain, gate and substrate terminals and said gate terminal being responsive to said first logic signal and said drain terminal being connected to said output terminal; a second P-channel enhancement mode, MOSFET having source, drain, gate and substrate terminals and having said drain terminal of said second P-channel MOSFET connected to the source terminal of said first P-channel MOSFET and said source of said second P-channel MOSFET connected to said first voltage level; said substrate terminal of said first P-channel MOSFET being connected to said substrate terminal of said second P-channel MOSFET and both being connected to said first voltage level; said gate terminal of said second P-channel MOSFET being responsive to said second logic signal; and said first logic signal and said second logic signal being equal to said second voltage level whereby, said first P-channel MOSFET and said second P-channel MOSFET are activated for connecting said output terminal to said first volTage level and charge carriers have a charge path from said first voltage level.
Claim 2
Dependent Claim
252 words
A CMOS exclusive NOR circuit comprising: a source of potential having a first voltage level and a second voltage level and said second voltage level being more negative than said first voltage level; a first input logic terminal and a second second input terminal; a first logic signal applied to said first terminal and a second logic signal applied to said second terminal; an output terminal; a first current charging and discharging path including said output terminal; a first P-channel, enhancement mode, MOSFET having source, drain, gate and substrate terminals and said gate terminal being responsive to said first logic signal and said drain terminal being connected to said output terminal; a second P-channel enhancement mode, MOSFET having source, drain, gate and substrate terminals and having said drain terminal of said second P-channel MOSFET connected to the source terminal of said first P-channel MOSFET and said source of said second P-channel MOSFET connected to said first voltage level; said substrate terminal of said first P-channel MOSFET being connected to said substrate terminal of said second P-channel MOSFET and both being connected to said first voltage level; said gate terminal of said second P-channel MOSFET being responsive to said second logic signal; and said first logic signal and said second logic signal being equal to said second voltage level whereby, said first P-channel MOSFET and said second P-channel MOSFET are activated for connecting said output terminal to said first volTage level and charge carriers have a charge path from said first voltage level.
Claim 3
Dependent Claim
33 words
A CMOS exclusive NOR circuit as recited in claim 1 and further comprising; a capacitive device connected to said output terminal for being charged to the voltage level of said first voltage level.
Claim 4
Dependent Claim
121 words
A CMOS exclusive NOR circuit as recited in claim 1, and further comprising; a second charging and discharging path comprising a first N-channel enhancement mode MOSFET having source, drain, gate and substrate terminals and having said source terminal connected to said output terminal, and said drain terminal connected to said first input logic signal terminal and said gate terminal being responsive to said second input logic signal, and said substrate terminal being connected to said second voltage level; and said first logic signal being at said second voltage level and said second logic signal being at said first voltage level, whereby; said first N-channel MOSFET is activated for forming a discharging path from said output terminal to said first input terminal.
Claim 5
Dependent Claim
33 words
A CMOS exclusive NOR circuit as recited in claim 3, and further comprising: a capacitive device connected to said output terminal for discharging to said voltage level of said first input logic signal.
Claim 6
Dependent Claim
139 words
A CMOS exclusive NOR circuit as recited in claim 3, and further comprising: a control signal being the complement of one of said logic signals; a third charging and discharging path comprising a third P-channel, enhancement mode MOSFET having source, drain gate and substrate terminals and said drain terminal being connected to said drain terminal of said first N-channel MOSFET, and said source terminal being connected to said output terminal, and said substrate terminal being connected to said first voltage level, and said gate electrode being responsive to said complement signal of said second logic signal; and said first logic signal being at said second voltage level and said second logic signal being at said first voltage level, whereby said first N-channel MOSFET is activated for forming a discharging path from said output terminal to said first input terminal.
Claim 7
Dependent Claim
33 words
A CMOS exclusive NOR circuit as recited in claim 5, and further comprising: a capacitive device connected to said output terminal for discharging to said voltage level of said first input logic signal.
Claim 8
Dependent Claim
40 words
A CMOS exclusive NOR circuit as recited in claim 6, wherein said third P channel MOSFET being activated by said complement signal of said second logic input signal for forming a parallel current path with said first N channel MOSFET.
Claim 9
Dependent Claim
56 words
A CMOS exclusive NOR circuit as recited in claim 5, wherein said second logic signal being at said first voltage level, whereby; said first N channel MOSFET and said third P channel MOSFET are simultaneously activated for sharing said current in said third charging and discharging path from said output terminal to said first input terminal.
Claim 10
Dependent Claim
31 words
A CMOS exclusive NOR circuit as recited in claim 8, and further comprising: a capacitive device connected to said output terminal for being discharged to a plurality of second voltage levels.
Claim 11
Dependent Claim
196 words
A CMOS exclusive NOR circuit as recited in claim 3, and further comprising: a control signal being the complement of one of said logic signals; a third charging and discharging path comprising a second N-channel, enhancement mode, MOSFET having source, drain, gate and substrate terminals and said drain terminal being connected to said second logic signal input terminal, and said gate terminal being connected to said first logic signal input terminal, and said substrate terminal being connected to said second voltage level and said source terminal being connected to said output terminal; and a third P-channel, enhancement mode, MOSFET having source, drain, gate and substrate terminals and said source terminal beIng connected to said second logic signal input terminal, and said drain terminal being connected to said output terminal, and said substrate terminal being connected to said first voltage level, and said gate terminal being connected to said complement signal of said first logic signal; and said first logic signal being now at said one voltage level, whereby; said second N-channel MOSFET and said third P channel MOSFET are activated for forming a discharging path from said second logic signal input terminal to said output terminal.
Claim 12
Dependent Claim
33 words
A CMOS exclusive NOR circuit as recited in claim 10, and further comprising: a capacitive device connected to said output terminal for discharging to the voltage level of said second input logic signal.
Claim 13
Dependent Claim
21 words
A CMOS exclusive NOR circuit as recited in claim 10, wherein: said second logic signal being at said second voltage level.
Claim 14
Dependent Claim
33 words
A CMOS exclusive NOR circuit as recited in claim 10, and further comprising: a capacitive device connected to said output terminal for discharging to the voltage level of said second input logic signal.
Claim 15
Dependent Claim
53 words
A CMOS exclusive NOR circuit as recited in claim 11, and further comprising: a fourth charging path comprising; said first N-channel MOSFET being activated and forming a charging path to said first input logic level terminal from said output terminal whereby said capacitive device is discharged to a plurality of second voltage levels.
Claim 16
Dependent Claim
118 words
A CMOS exclusive NOR circuit as recited in claim 5, and further comprising: a fourth charging and discharging path comprising, a second N-channel, enhancement mode, MOSFET having source, drain, gate and substrate terminals and having its drain terminal connected to said second logic signal input terminal, and having its source terminal connected to said output signal output terminal, and having its substrate terminal connected to said second voltage level, and having its gate terminal connected to said first logic signal input terminal; and said first logic signal now being at said first voltage level, whereby said second N-channel MOSFET being activated for forming said sixth charging path between said second logic signal input terminal and said output terminal.
Claim 17
Dependent Claim
33 words
A CMOS exclusive NOR circuit as recited in claim 15, and further comprising: a capacitive device connected to said output terminal for charging to the voltage level of said second input logic signal.
Claim 18
Dependent Claim
42 words
A CMOS exclusive NOR circuit as recited in claim 15 wherein: said second logic signal being at said second voltage level; and said complement of said second logic signal being at said first voltage level for turning off said third P-channel MOSFET.
Claim 19
Dependent Claim
33 words
A CMOS exclusive NOR circuit as recited in claim 17, and further comprising: a capacitive device connected to said output terminal for discharging to said voltage level of said second input logic signal.
Claim 20
Dependent Claim
169 words
A CMOS exclusive NOR circuit as recited in claim 10, wherein said complement signal of said first logic signal being generated by an inverter circuit formed integral therewith, said inverter circuit comprising: a fourth P-channel, enhancement mode, MOSFET having source, drain, gate and substrate terminals and said source terminal being connected to said first voltage level, and said gate terminal being connected to said first logic signal input terminal and said substrate terminal being connected to said first voltage level; and a third N-channel, enhancement mode, MOSFET having source, drain, gate and substrate terminals, and said drain terminal being connected to a junction formed by said drain terminal of said fourth P-channel MOSFET and said gate terminal of said third channel MOSFET and said substrate terminal being connected to said drain terminal and both being connected to said second voltage level, and said gate terminal being connected to said first logic signal input terminal, whereby; said cOmplement signal of said first logic signal is available at said first junction.
Claim 21
Dependent Claim
174 words
A CMOS exclusive NOR circuit as recited in claim 15, wherein said complement signal of said second logic signal being generated by an inverter circuit formed integral therewith, said inverter circuit comprising: a fourth P-channel, enhancement mode, MOSFET, having source, drain, gate and substrate terminals and said source terminal being connected to said first voltage level, and said gate terminal being connected to said second logic signal input terminal, and said substrate terminal being connected to said first voltage level; and a third N-channel, enhancement mode MOSFET having source, drain, gate and substrate terminals, and said drain terminal being connected to a second junction formed by said drain terminal of said fourth P-channel MOSFET and said gate terminal of said third P-channel MOSFET and said substrate terminal being connected to said source terminal of said same MOSFET and both being connected to said second voltage level, and said gate terminal being connected to said second logic signal input terminal, whereby; said complement signal of said second logic signal is available as said second junction.
References Cited (Backward Citations)
US3541353A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-08-08 | 1976-02-07 | 1976-08-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-08-08 | 1980-02-07 | 1980-08-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-08-08 | 1984-02-07 | 1984-08-08 | $7700.00 | Window Closed / Lapsed |