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US3683164A Expired / Lapsed US ⏱️ 0.0 years remaining

Analog calculation apparatus for performing convolution

Assignee: Hitachi Ltd
•
Filing: 1969-04-16
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Granted: 1972-08-08
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Expires: 1989-04-16
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Abstract

Abstract An analog calculating apparatus in which an analog signal, which is a function of time and has been ( permanently ) recorded on a first channel track of a tape recorder is read out during a first run of the tape of the tape recorder and is multiplied by a first one of a set of coefficients at equal time intervals in a coefficient multiplier and recorded on a second channel track of the tape recorder. During the second run of the tape the analog signal read out from the first track is then multiplied by the second coefficient in the coefficient multiplier and added through an adder to the product read out from the second track, and the sum is then recorded on the second track immediately after the second track is erased, and this latter operation is then repeated.

Inventors

  • 👤 Shigeo Minami

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-05 04:41
CPC Classifications
G; G06; G06G; G06G7/00; G06G7/12; G06G7/19; G06G7/1914

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 410 words
An analog computer apparatus comprising: first means for supplying a first analog data signal; second means, responsive to said first means, for successively generating a plurality of second analog data signals identical to said first analog data signal but being successively delayed with respect to each other and said first analog data signal by successive predetermined periods of time, said second means comprising a first track of an analog storage tape recorder, a first record head coupled to said first means for supplying said first analog data signal to said first track, a reproduction head spaced apart by a predetermined distance from said record head, so that when said first track is moved in the direction from said reproduction head toward said record head, after said first analog data signal has been stored on said first track, said reproduction head will produce said first signal delayed with respect to the reproduction of said first signal during a previous pass of said track; third means, responsive to said second means, and being coupled to said reproduction head, for multiplying each of said successively generated second analog data signals by predetermined weighting coefficients, each multiplication corresponding to an individual pass of said tape past said reproduction head, to produce third analog signals; and fourth means, responsive to said third means, for generating an analog output signal representative of the convolution of said first analog data signal with a signal representative of said weighting coefficients, including an adder circuit, having a first input connected to the output of said third means, a second storage tape track coupled to the output of said adder circuit through a record head, whereby the output of said adder circuit will be recorded on said second track, a reproduction head spaced apart from said record head a predetermined distance, so that when said second track passes by said reproduction head in the direction of said record head, the signal on said second track will be detected by said reproduction head and an output will be produced therefrom, and means for coupling the output of said reproduction head to a second input of said adder circuit, whereby the signal stored on said second tape track will be successively added with the output of said coefficient multiplier, and further including means for coupling the output of said reproduction head associated with said second track to an output terminal whereby said analog output signal representative of said convolution will be reproduced.
Claim 2
Dependent Claim 410 words
An analog computer apparatus comprising: first means for supplying a first analog data signal; second means, responsive to said first means, for successively generating a plurality of second analog data signals identical to said first analog data signal but being successively delayed with respect to each other and said first analog data signal by successive predetermined periods of time, said second means comprising a first track of an analog storage tape recorder, a first record head coupled to said first means for supplying said first analog data signal to said first track, a reproduction head spaced apart by a predetermined distance from said record head, so that when said first track is moved in the direction from said reproduction head toward said record head, after said first analog data signal has been stored on said first track, said reproduction head will produce said first signal delayed with respect to the reproduction of said first signal during a previous pass of said track; third means, responsive to said second means, and being coupled to said reproduction head, for multiplying each of said successively generated second analog data signals by predetermined weighting coefficients, each multiplication corresponding to an individual pass of said tape past said reproduction head, to produce third analog signals; and fourth means, responsive to said third means, for generating an analog output signal representative of the convolution of said first analog data signal with a signal representative of said weighting coefficients, including an adder circuit, having a first input connected to the output of said third means, a second storage tape track coupled to the output of said adder circuit through a record head, whereby the output of said adder circuit will be recorded on said second track, a reproduction head spaced apart from said record head a predetermined distance, so that when said second track passes by said reproduction head in the direction of said record head, the signal on said second track will be detected by said reproduction head and an output will be produced therefrom, and means for coupling the output of said reproduction head to a second input of said adder circuit, whereby the signal stored on said second tape track will be successively added with the output of said coefficient multiplier, and further including means for coupling the output of said reproduction head associated with said second track to an output terminal whereby said analog output signal representative of said convolution will be reproduced.
Claim 3
Dependent Claim 26 words
An apparatus according to claim 1, further including a filter and a sensitivity adjusting circuit switchably connected to the reproduction head of said second tape track.
Claim 4
Dependent Claim 70 words
An apparatus according to claim 2, further including means for substantially eliminating the effects of recorder noise from said convolution signal including a third and fourth tape recorder channel corresponding to a third and a fourth tape recorder track, respectively connected in series with each of the first and second channels corresponding to said first and second tape tracks, for recording only the noise stored on the tape storage tracks.
Claim 5
Dependent Claim 66 words
An apparatus according to claim 3, further including a second adder circuit connected between said adder circuit of said fourth means and said third and fourth channels for combining the signals produced therein at a first pair of inputs thereof and for inversely adding thereto the output of said adder circuit of said fourth means, whereby said noise signals will be cancelled from said convolution signal.
Claim 6
Dependent Claim 35 words
An apparatus according to claim 4, wherein said third channel further includes an additional coefficient multiplying means for successively weighting the signals produced by said third channel to be delivered to said second adder circuit.

References Cited (Backward Citations)

US2794965A Cited
US2836359A Cited
US2922965A Cited
US3100297A Cited
US3240919A Cited
US3310665A Cited
US3303335A Cited
US3459928A Cited
US3418625A Cited
US3435195A Cited
US3489848A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1975-08-08 1976-02-07 1976-08-08 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1979-08-08 1980-02-07 1980-08-08 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1983-08-08 1984-02-07 1984-08-08 $7700.00 Window Closed / Lapsed

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