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US3681708A
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Pseudo-random frequency generator
Assignee: Bendix Corp
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Filing: 1969-04-29
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Granted: 1972-08-01
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Expires: 1989-04-29
Abstract
Abstract A binary pseudo-random frequency generator in which a shift register is continuously strobed by a clock and has its informational content altered in accordance with its acquired state. A variable count divider counts down to zero from a number set therein from information received from the shift register at the divider zero count in response to frequency signals received from a voltage controlled oscillator. Divider zero counts are also compared in a phased lock loop with a reference frequency to set the voltage controlled oscillator frequency.
Inventors
- 👤 Merlin E Olmstead
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 12:22
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/58; G06F7/582; G06F7/584; G06F2207/00; G06F2207/58; G06F2207/581; G06F2207/583
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
123 words
Means for generating pseudo-random electrical frequencies coMprising: means for generating clock pulses; a binary number generator having output taps, for generating upon said output taps a random-like sequence of binary numbers in response to said clock pulses; binary means for counting electrical frequency signals; means responsive to predetermined counts of said counting means for generating first electrical signals; means responsive to said first electrical signals for entering a binary number related to an instantaneous one of said randomlike sequence of binary numbers into said counting means; and, a phase locked loop including said counting means and said first electrical signal generating means, for generating said pseudorandom electrical frequencies in response to said first electrical signals, said frequencies being counted by said counting means.
Claim 2
Dependent Claim
123 words
Means for generating pseudo-random electrical frequencies coMprising: means for generating clock pulses; a binary number generator having output taps, for generating upon said output taps a random-like sequence of binary numbers in response to said clock pulses; binary means for counting electrical frequency signals; means responsive to predetermined counts of said counting means for generating first electrical signals; means responsive to said first electrical signals for entering a binary number related to an instantaneous one of said randomlike sequence of binary numbers into said counting means; and, a phase locked loop including said counting means and said first electrical signal generating means, for generating said pseudorandom electrical frequencies in response to said first electrical signals, said frequencies being counted by said counting means.
Claim 3
Dependent Claim
76 words
Frequency generating means as recited in claim 1 wherein said binary number generator comprises: a shift register having a plurality of output taps, said random-like sequence of binary numbers appearing on preselected ones thereof, a shift pulse terminal to which said clock pulses are applied, and a data input terminal; and, gating means having input terminals connected to other preselected of said output taps for applying a digital bit to said shift register data input terminal.
Claim 4
Dependent Claim
39 words
Frequency generating means as recited in claim 2 wherein said shift register comprises a first cascade of binary elements connected as a shift register and said counting means comprises a second cascade of binary elements connected as a counter.
Claim 5
Dependent Claim
63 words
Frequency generating means as recited in claim 1 wherein said phase locked loop comprises in addition to said counting means and said first signal generating means; a source of reference frequencies; a phase detector receiving as inputs said reference frequencies and said first electrical signals for generating an error signal; and, means responsive to said error signal for generating said pseudo-random electrical frequencies.
Claim 6
Dependent Claim
65 words
Frequency generating means as recited in claim 1 wherein said phase locked loop comprises in addition to said counting means and said first electrical signal generating means: a source of reference frequencies; a phase detector responsive to said reference frequencies and said first signal for generating a voltage signals; and, voltage controlled oscillator means responsive to said voltage signal for generating said pseudo-random electrical frequencies.
Claim 7
Dependent Claim
30 words
Frequency generating means as recited in claim 5 with additionally means for resetting said voltage controlled oscillator, said binary number generator and said counting means to a predetermined initial state.
Claim 8
Dependent Claim
25 words
Frequency generating means as recited in claim 5 wherein said voltage controlled oscillator means is constrained to generate electrical frequencies within a predetermined frequency band.
Claim 9
Dependent Claim
61 words
Means for generating pseudo-random electrical frequencies comprising: means for generating clock pulses; a binary number generating means having output taps, for generating upon said output taps a random-like sequence of binary numbers in response to said clock pulses; and, phase locked loop means for generating said pseudo-random electrical frequencies in response to selected ones of said random-like sequence of binary numbers.
Claim 10
Dependent Claim
61 words
Means for generating pseudo-random electrical frequencies comprising: means for generating clock pulses; a binary number generating means having output taps, for generating upon said output taps a random-like sequence of binary numbers in response to said clock pulses; and, phase locked loop means for generating said pseudo-random electrical frequencies in response to selected ones of said random-like sequence of binary numbers.
Claim 11
Dependent Claim
32 words
Means for generating pseudo-random electrical frequencies as recited in claim 8 with additionally means for resetting said binary number generating means and said phase locked loop means to a predetermined initial state.
Claim 12
Dependent Claim
107 words
Means for generating pseudo-random electrical frequencies as recited in claim 8 wherein said phase locked loop means comprises: means for generating an error signal; means responsive to said error signal for generating said pseudo-random electrical frequencies; means for counting from a preset number to a predetermined number in response to said pseudo-random electrical frequencies; means for generating an elecTrical signal upon said counting means attaining said predetermined number, said means for generating an error signal being responsive to said electrical signal; and, gating means responsive to said electrical signal for setting a number related to one of said random-like sequence of binary numbers into said counting means.
Claim 13
Dependent Claim
51 words
Means for generating pseudo-random electrical frequencies as recited in claim 10 wherein said means for generating an error signal comprises: a source of reference frequencies; and, a phase detector responsive to said reference frequencies and said electrical signal for generating said error signal, said error signal comprising a voltage level signal.
Claim 14
Dependent Claim
31 words
Means for generating pseudo-random electrical frequencies as recited in claim 11 wherein said means for generating said pseudo-random electrical frequencies comprises a voltage controlled oscillator controlled by said voltage level signal.
Claim 15
Dependent Claim
58 words
Means for generating pseudo-random electrical frequencies as recited in claim 10 wherein said gating means comprises a plurality of dual input coincidence gates, all said gates receiving as one input thereto said electrical signal and each said gate receiving as a second input thereto the binary bit appearing on one of said binary number generating means output taps.
Claim 16
Dependent Claim
55 words
Means for generating pseudo-random electrical frequencies as recited in claim 13 wherein said counting means comprises a cascade of binary elements arranged to count from a preset binary number to a predetermined binary number in response to said pseudo-random electrical frequencies, said preset binary number being preset into said counting means from said gating means.
Claim 17
Dependent Claim
42 words
Means for generating pseudo-random electrical frequencies as recited in claim 14 wherein each said counting means binary element includes a set terminal and each of said plurality of dual input coincidence gates is connected to a predetermined one of said set terminals.
Claim 18
Dependent Claim
30 words
Means for generating pseudo-random electrical frequencies as recited in claim 15 wherein said gating means additionally comprises means for applying said electrical signal directly to other of said set terminals.
Claim 19
Dependent Claim
33 words
Means for generating pseudo-random electrical frequencies as recited in claim 16 with additionally means for resetting said voltage controlled oscillator, said counting means and said binary number generating means to predetermined initial states.
References Cited (Backward Citations)
US3484712A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-08-01 | 1976-01-31 | 1976-08-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-08-01 | 1980-01-31 | 1980-08-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-08-01 | 1984-01-31 | 1984-08-01 | $7700.00 | Window Closed / Lapsed |