Digital adf tuning indicator

Claim 2

A tuning indicator for an ADF system including a local oscillator adapted to be tuned to a frequency upwardly off-set by a predetermined amount from the frequency to be received, said indicator comprising; timing means, means for counting the number of cycles of the local oscillator output during a predetermined period; display means coupled to said counting means to provide a digital read-out of said stored count; and off-set logic means connected to said counting means and responsive to accumulation of a count corresponding to said upward off-set at the beginning of a count period to reset said counting means to a count of zero.

Claim 3

A tuning indicator for an ADF system including a local oscillator adapted to be tuned to a frequency upwardly off-set by a predetermined amount from the frequency to be received, said indicator comprising: timing means for establishing an operating cycle comprising a count period followed by a display period; means for counting the number of cycles of the local oscillator output during said count period; temporary storage means coupled to said counting means and said timing means, said temporary storage means being operative at the beginning of said display period to store a representation of the count contained in said counting means at the end of the immediately preceeding count period; display means coupled to said temporary storage means to provide a digital read-out of said stored count; and off-set logic means connected to said counting means and responsive to accumulation of a count corresponding to said upward off-set at the beginning of a count period to reset said counting means to a count of zero.

Claim 4

A tuning indicator for an ADF system including a local oscillator adapted to be tuned to a frequency upwardly off-set by a predetermined amount from the frequency to be received, said indicator comprising: timing means for establishing an operating cycle comprising a count period followed by a display period; means for counting the number of cycles of the local oscillator output during said count period; temporary storage means coupled to said counting means and said timing means, said temporary storage means being operative at the beginning of said display period to store a representation of the count contained in said counting means at the end of the immediately preceeding count period; display means coupled to said temporary storage means to provide a digital read-out of said stored count; and off-set logic means connected to said counting means and responsive to accumulation of a count corresponding to said upward off-set at the beginning of a count period to reset said counting means to a count of zero.

Claim 5

An indicator as defined in claim 2 wherein said upward off-set equals 142.5 KHz and wherein said operating cycle is of 20 millisecond duration, with a 10 millisecond count period immediately followed by a 10 millisecond display period.

Claim 6

An indicator according to claim 2 wherein said display means comprises a plurality of seven bar segment illuminated indicators.

Claim 7

An indicator according to claim 4 wherein said data stored in said temporary storage means is in a binary coded decimal format and wherein said display means includes decoder means for converting said binary coded decimal format to the seven segment code format for each decimal digit to be displayed.

Claim 8

An indicator according to claim 2 wherein said off-set logic comprises means responsive to accumulation of said off-set count to generate a control pulse; bistable circuit means, said bistable circuit means being operative in response to said control pulse to switch from a first to a second state; means responsive to establishment of said second binary circuit state for returning said counting means to a count of zero; and further including means in said timing means to generate a reset signal at the end of said display period, said bistable circuit means being responsive to said reset signal to switch from said second to said first state.

Claim 9

An indicator according to claim 6 further including means responsive to said reset signal to return said counter to a count of zero irrespective of the state of said bistable circuit means.

Claim 10

An indicator according to claim 2 wherein said timing means comprises primary clock means for generating a high frequency pulse train; divider means coupled to said clock means to generate a low frequency square wave, the first and second half cycles of said squarewave representing said counting period, and the display period respectively of said operating cycle; first logic means responsive to the beginning of said second half cycle to generate a first control signal of duration less than the duration of said second half cycle; second logic means responsive to coMpletion of a predetermined portion of said second half cycle longer than the duration of said first control signal to generate a second control signal continuing to the end of said second half cycle; means responsive to said first control signal to operate said temporary storage means; and means responsive to said second control signal to return said counting means to a count of ''''0''''.

Claim 11

An indicator according to claim 8 wherein said first and second logic means each comprise combinational logic elements coupled to said divider means.

Claim 12

An indicator according to claim 2 wherein said counting means comprises a plurality of series connected decade counter stages, each stage providing a binary coded decimal signal output representative of the count state thereof; and further including gating means coupled to the output of said local oscillator and responsive to establishment of said counting period to couple said local oscillator output to the input of said first decade counter stage;

Claim 13

An indicator according to claim 10 further including a one bit binary counter coupled to the output of the last of said series connected decade counter stages.

Claim 14

An indicator according to claim 11 wherein said temporary storage means comprises a first group of multiple bit latching circuits, each of said latching circuits being connected to the output of one of said decade counter stages, and a further single bit latching circuit connected to the output of said binary counter stage, said latching circuits being operative at the beginning of the display period of each operating cycle to store the count then present in the respective decade and binary counter stages.

Claim 15

An indicator according to claim 12 wherein said timing means comprises primary clock means for generating a high frequency pulse train; divider means coupled to said clock means to generate a low frequency squarewave, the first and second half cycles of said square-wave representing said counting period, and the display period respectively of said operating cycle; means coupling said squarewave to control said gating means; first logic means responsive to the beginning of said second half cycle to generate a first control signal of duration less than the duration of said second half cycle; second logic means responsive to completion of a predetermined portion of said second half cycle longer than the duration of said first control signal to generate a second control signal continuing to the end of said second half cycle; means responsive to said first control signal to actuate said latching means to store the count in said decade counter stages at that time, and means responsive to said second control signal to reset said decade counting stages and said one bit binary counter.

Claim 16

An indicator according to claim 13 wherein said display means comprises a plurality of seven bar-segment display elements, one of said display elements being associated with each of said latching circuits; a plurality of binary coded decimal to seven segment decoders, each respectively coupling one of said four-bit latching circuits to the associated display element, and further means coupling the output of said one-bit latching circuit to another of said seven bar segment display elements.

Claim 17

An indicator according to claim 12 wherein the number of latching circuits is less than the number of decade counter stages.