Filtering method and a circuit arrangement for carrying out the filtering method

Claim 3

A circuit arrangement for filtering an AF band out of a wide band input signal in a time-division multiplex switching system comprising means receiving an input signal, means for routing said input signal over each of a plurality of parallel transmission paths, means including electronic clock-controlled switches in each parallel transmission path for feeding the input signal out of phase, said signal being delayed one half cycle in a first path and an additional one half cycle in each successive path and in each case for a full cycle duration to each of a plurality of integrators, second clock-controlled electronic switches via which the output of one integrator is in each case alternately connected to the output of the circuit arrangement during a half-cycle after the opening of the associated first switch.

Claim 4

A circuit arrangement for filtering an AF band out of a wide band input signal in a time-division multiplex switching system comprising means receiving an input signal, means for routing said input signal over each of a plurality of parallel transmission paths, means including electronic clock-controlled switches in each parallel transmission path for feeding the input signal out of phase, said signal being delayed one half cycle in a first path and an additional one half cycle in each successive path and in each case for a full cycle duration to each of a plurality of integrators, second clock-controlled electronic switches via which the output of one integrator is in each case alternately connected to the output of the circuit arrangement during a half-cycle after the opening of the associated first switch.

Claim 5

A circuit arrangement according to claim 2 in which two integrators are coupled to the input signal in parallel and which, out of phase in relation to one another by one half cycle, are reset after each cycle, and two associated electronic switches via which the signal integral is transmitted to a storage at the end of each integration cycle and immediately prior to the resetting of the integrator.

Claim 6

A circuit arrangement according to claim 2, in which, an equalizer is connected to each filter stage, said equalizer compensating for undesired frequency responses of the filter stage in the passband.

Claim 7

A circuit arrangement according to claim 2, in which, several filter stages of equal integration duration are connected in series.

Claim 8

A circuit arrangement according to claim 2, in which several filter stages of unequal integration duration are connected in series.

Claim 9

A circuit arrangement according to claim 4, in which a common equalizer is connected to a ladder of filter stages.

Claim 10

A circuit arrangement according to claim 2, in which an equalizer is connected in parallel to said filter, and one input of a summing amplifier is connected to the output of said filter and the other input of said summing amplifier is connected to the output of said equalizer via a coefficienT potentiometer.

Claim 11

A circuit arrangement according to claim 8, in which the equalizer is designed as a controlled switch filter, and in which a differential amplifier (DV) combines the voltages of two capacitors to form the output signal of said equalizer.

Claim 12

A method of filtering an A.F. band out of a wideband input signal as claimed in claim 1, in which the time intervals are selected to have a duration corresponding to one-half the period of said signals near the center of said A.F. band, and the succesively obtained integral values are separately stored for the double integration duration.

Claim 13

A circuit arrangement for filtering an AF band out of a wide band input signal in a time-division multiplex switching system comprising means receiving an input signal, means for routing said input signal over each of a plurality of parallel transmission paths, means including an integrator in each parallel path to which the input signal is constantly applied and which is reset by clock control after each of a plurality of fixed periods of time, a plurality of buffer stores, an electronic switch associated with each buffer store to which the integral value from one of said integrators is alternately fed shortly before the resetting of said integrator, and a summing element which forms the output signal from said alternately stored integral values.

Claim 14

A circuit arrangement for filtering an AF band out of a wide band input signal in a time-division multiplex switching system comprising means receiving an input signal, means for routing said input signal over each of a plurality of parallel transmission paths, means including an integrator in each parallel path to which the input signal is constantly applied and which is reset by clock control after each of a plurality of fixed periods of time, a plurality of buffer stores, an electronic switch associated with each buffer store to which the integral value from one of said integrators is alternately fed shortly before the resetting of said integrator, and a summing element which forms the output signal from said alternately stored integral values.

Claim 15

A circuit arrangement according to claim 11, in which an equalizer compensating for the undesired frequency response is connected to said filter stage.

Claim 16

A circuit arrangement according to claim 11, in which several filter stages of equal integration duration are connected in series.

Claim 17

A circuit arrangement according to claim 11, in which several filter stages of unequal integration duration are connected in series.

Claim 18

A circuit arrangement according to claim 13, in which a common equalizer is connected to a ladder of filter stages.

Claim 19

A circuit arrangement according to claim 11, in which an equalizer is connected in parallel to said filter, and one input of a summing amplifier is connected to the output of said filter and the other input of said summing amplifier is connected to the output of said equalizer via a coefficient potentiometer.

Claim 20

A circuit arrangement according to claim 16, in which said equalizer is designed as a controlled switch filter in which the input voltage with the double frequency of the frequency of infinite attenuation of said filter is alternately fed to one of two capacitors and in which a differential amplifier combines the voltages of said capacitors to form the output signal of said equalizer.

Claim 21

A circuit arrangement for filtering an AF band out of a wide band input signal in a time-division multiplex switching system comprising means receiving an input signal, means including electronic clock-controlled switches for feeding the input signal out of phase by one half cycle and in each case for a full cycle duration to each of a plurality of integrators, second clock-controlled electronic switches via which the output of one integrator is in each case alternately connected to the output of the circuit arrangement during a half-cycle after the opening of the associated first switch, an equalizer connected in parallel to said integrators, a first plurality of input terminals of a summing amplifier connected to the outputs of said integrators, another input of said summing amplifier connected to the output of said equalizer via a coefficient potentiometer, said equalizer including means functioning as a controlled switch fileter, and said equalizer including a differential amplifier to combine the voltages of two capacitors to form the output signal of said equalizer.

Claim 22

A circuit arrangement for filtering an AF band out of a wide band input signal in a time-division multiplex switching system comprising means receiving an input signal, means including electronic clock-controlled switches for feeding the input signal out of phase by one half cycle and in each case for a full cycle duration to each of a plurality of integrators, second clock-controlled electronic switches via which the output of one integrator is in each case alternately connected to the output of the circuit arrangement during a half-cycle after the opening of the associated first switch, an equalizer connected in parallel to said integrators, a first plurality of input terminals of a summing amplifier connected to the outputs of said integrators, another input of said summing amplifier connected to the output of said equalizer via a coefficient potentiometer, said equalizer including means functioning as a controlled switch fileter, and said equalizer including a differential amplifier to combine the voltages of two capacitors to form the output signal of said equalizer.

Claim 23

A circuit arrangement for filtering an AF band out of a wide band input signal in a time-division multiplex switching system comprising means receiving an input signal, means including an integrator to which the input signal is constantly applied and which is reset by clock control after each Of a plurality of fixed periods of time, two buffer stores, an electronic switch associated with each buffer store to which the integral value is alternately fed shortly before the resetting of said integrator, a summing amplifier to form an output signal from said alternately stored integral values, an equalizer connected in parallel to said integrator, means connecting one input of said summing amplifier to the output of said integrator, and means connecting another input of said summing amplifier to the output of said equalizer via a coefficient potentiometer, said equalizer including a controlled switch filter in which the input voltage with the double frequency of the frequency of infinite attenuation of said filter is alternately fed to one of two capacitors and the differential amplifier serving to combine the voltages of said capacitors to form the output signal of said equalizer.

Claim 24

A circuit arrangement for filtering an AF band out of a wide band input signal in a time-division multiplex switching system comprising means receiving an input signal, means including an integrator to which the input signal is constantly applied and which is reset by clock control after each Of a plurality of fixed periods of time, two buffer stores, an electronic switch associated with each buffer store to which the integral value is alternately fed shortly before the resetting of said integrator, a summing amplifier to form an output signal from said alternately stored integral values, an equalizer connected in parallel to said integrator, means connecting one input of said summing amplifier to the output of said integrator, and means connecting another input of said summing amplifier to the output of said equalizer via a coefficient potentiometer, said equalizer including a controlled switch filter in which the input voltage with the double frequency of the frequency of infinite attenuation of said filter is alternately fed to one of two capacitors and the differential amplifier serving to combine the voltages of said capacitors to form the output signal of said equalizer.