Carry transfer circuit for a parallel binary adder

Claim 1

A circuit arrangement for the production of a negated group transfer with the aid of negation type logic circuits with a parallel adder which is divided into groups and the group transfer is formed in parallel, said arrangement comprising: a plurality of adder stages as an adder group, each said stage having an input for receiving a transfer signal from a lower value adder stage, inputs for receiving input operand signals, an equivalent output and a disjunctive output; a corresponding plurality of negation type logic circuits individually assigned to said adder stages and each having an output connected in common with like other outputs of said logic circuits, an input connected to the disjunctive output of the assigned adder stage, individual inputs connected to the equivalent outputs of the adder stages of higher value than the assigned adder stage; and an additional negation type logic circuit having an output connected to the commonly connected outputs of said plurality of logic circuits to provide a transfer output to a subsequent transfer group, an input to receive a transfer signal from a lower value adder group, and a plurality of inputs individually connected to the equivalent outputs of each said adder stage.