Domain propagation circuit

Claim 2

A domain propagation arrangement comprising a sheet of material in which single wall domains can be moved, and a magnetically soft overlay juxtaposed with a surface of said sheet, said overlay having a geometry to define a 2n+k stage first register for moving single wall domains through a first interaction point from input to output positions in response to a reorienting in-plane field, said overlay at said interaction point having a geometry such that said channel folds back upon itself forming first, second, and third sections, said overlay at said interaction point also having a geometry to allow a domain into said third section only when a domain occurs in the like stages of said first and second sections.

Claim 3

An arrangement in accordance with claim 1 wherein each of said first and second sections comprises n of said 2n+k stages.

Claim 4

An arrangement in accordance with claim 2 wherein said overlay also defines a second register like said first for synchronous operation therewith in response to said reorienting in plane field.

Claim 5

An arrangement in accordance with claim 2 including input means for providing in said first section of said first register a first domain pattern representative of the presence and absence of signals in n lines.

Claim 6

An arrangement in accordance with claim 3 including input means adapted to provide in the first section of said first and second registers first and second complementary domain patterns representative of the presence and absence of signals in n lines.

Claim 7

An arrangement in accordance with claim 5 wherein said input means comprises first and second arrangements of magnetically soft overlay elements for defining first and second n stage input registers, said elements having geometries to define first and second laterally displaced stable positions for a domain in each of said stages, domain generating means for providing a domain in each of said n stages of said first section of said first register, a first control electrical conductor coupled serially to said n stages of said first register adapted to displace domains from said first register to said first input register when pulsed, n electrical conductors coupled to the n stages of said second input register for displacing corresponding domains from said first to said second register when signals are applied thereto, and second and third electrical conductors coupled serially to the n stage of said first and second registers respectively for displacing domains from said first and second input registers to corresponding stages of said first section of each of said first and second registers respectively when pulsed.

Claim 8

An arrangement in accordance with claim 1 wHerein said overlay defines a compressor arrangement in said third section.

Claim 9

An arrangement in accordance with claim 3 wherein said overlay defines a compressor arrangement in said third section of each of said first and second registers.

Claim 10

An arrangement in accordance with claim 8 wherein said overlay has a geometry for defining first and second domain annihilators at the terminus of said second sections of said first and second registers respectively.

Claim 11

An arrangement in accordance with claim 9 wherein said third sections of said first and second registers include first and second outputs and said overlay has a geometry for defining adjacent said outputs, respectively, first and second n stage closed loop registers for recirculating single wall domains in response to a reorienting in-plane field, said overlay also defining a compressor arrangement including a first stage of each of said closed loop registers for selectively transferring a domain between said closed loop registers.

Claim 12

An arrangement in accordance with claim 10 wherein said overlay defines first and second interaction points between said first and second closed loop registers and said third sections of said first and second shift registers at said output positions respectively, said overlay at the terminus of each of said third sections being of a geometry to move domains to said domain annihilator there in the absence of a domain in the first stage of the associated one of said first and second closed loop shift registers and to deflect a domain in said third section to the corresponding output in the presence of a domain in that first position.

Claim 13

A circuit for signaling first and second changes in condition for each of a set of lines, said circuit comprising first and second shift register channels including first and second output positions respectively, means responsive to a first scan signal for storing complementary first and second sets of representations of the condition of said lines in said first and second registers respectively, means responsive to a second scan signal for storing complementary third and fourth sets of representations of the conditions of said lines also in said first and second registers respectively, means responsive to each of said scan signals for advancing said sets of representations in said registers synchronously, means for comparing consecutive representations in said first and third sets and said second and fourth sets of representations for generating complementary first and second persistent line condition indications, and means responsive to one of said first or second persistent line indications for each of said consecutive lines of said set for signaling only when the other of said first or second second persistent line indications next occurs for that line.

Claim 14

A circuit for signaling first and second changes in condition for each of a set of lines, said circuit comprising first and second shift register channels including first and second output positions respectively, means responsive to a first scan signal for storing complementary first and second sets of representations of the condition of said lines in said first and second registers respectively, means responsive to a second scan signal for storing complementary third and fourth sets of representations of the conditions of said lines also in said first and second registers respectively, means responsive to each of said scan signals for advancing said sets of representations in said registers synchronously, means for comparing consecutive representations in said first and third sets and said second and fourth sets of representations for generating complementary first and second persistent line condition indications, and means responsive to one of said first or second persistent line indications for each of said consecutive lines of said set for signaling only when the other of said first or second second persistent line indications next occurs for that line.

Claim 15

A combination comprising a sheet of material in which single wall domains can be moved, a magnetically soft overlay juxtaposed with a surface of said sheet, said overlay having a geometry for defining first and second n stage closed loop registers for recirculating single wall domains in response to a reorienting in-plane field, said overlay also defining means including a first stage of each of said registers for selectively transferring a domain therebetween wherein said last-mentioned means comprises first and second domain propagation registers including first and second outputs respectively, said first and second outputs being in close proximity to said first and second closed registers at said outputs, respectively, said overlay at each of said outputs having a geometry for moving a domain in said first or second closed loop registers in a manner to interact with a domain in the associated propagation register to deflect said domains to the first stage of the other of said closed loop registers and to an associated one of said outputs.

Claim 16

A combination comprising a sheet of material in which single wall domains can be moved, a magnetically soft overlay juxtaposed with a surface of said sheet, said overlay having a geometry for defining first and second n stage closed loop registers for recirculating single wall domains in response to a reorienting in-plane field, said overlay also defining means including a first stage of each of said registers for selectively transferring a domain therebetween wherein said last-mentioned means comprises first and second domain propagation registers including first and second outputs respectively, said first and second outputs being in close proximity to said first and second closed registers at said outputs, respectively, said overlay at each of said outputs having a geometry for moving a domain in said first or second closed loop registers in a manner to interact with a domain in the associated propagation register to deflect said domains to the first stage of the other of said closed loop registers and to an associated one of said outputs.

Claim 17

A circuit for selectively signaling first and second changes in state in each of a plurality of linEs, said circuit comprising first and second shift register channels including first and second output positions respectively, means responsive to consecutive scan signals for forming complementary first and second persistent state indications for consecutive ones of said lines in said first and second channels respectively, means for sequentially moving said indications to said first and second output positions for generating first or second persistent state signals there, control means for sequentially enabling said first or second output positions for consecutive ones of said lines, and means responsive to each of said first or second persistent state indications for each of said lines operative upon said control means for next enabling the alternative output position for that line.

Claim 18

A circuit for selectively signaling first and second changes in state in each of a plurality of linEs, said circuit comprising first and second shift register channels including first and second output positions respectively, means responsive to consecutive scan signals for forming complementary first and second persistent state indications for consecutive ones of said lines in said first and second channels respectively, means for sequentially moving said indications to said first and second output positions for generating first or second persistent state signals there, control means for sequentially enabling said first or second output positions for consecutive ones of said lines, and means responsive to each of said first or second persistent state indications for each of said lines operative upon said control means for next enabling the alternative output position for that line.

Claim 19

A circuit for signaling first and second changes in the condition of each of a plurality of lines from a signal to a no-signal condition and from a no-signal to a signal condition respectively, said circuit comprising first and second shift register channels including first and second output positions respectively, means responsive to each of a sequence of command signals for storing a set of indications and the complements thereof representative of said line conditions in said first and second registers respectively and for advancing stored indications therein, means responsive to the presence of consecutive indications of like conditions for each of said lines for forming in said first and second registers respectively first and second indications of the persistence of a signal or no-signal condition for each of said lines for consecutive ones of said command signals and for advancing said persistence indications to said first and second output positions respectively, and means responsive to each of consecutive ones of said first and second persistence indications for enabling an output from only said second or first output position respectively for consecutive ones of said lines.

Claim 20

A circuit for signaling first and second changes in the condition of each of a plurality of lines from a signal to a no-signal condition and from a no-signal to a signal condition respectively, said circuit comprising first and second shift register channels including first and second output positions respectively, means responsive to each of a sequence of command signals for storing a set of indications and the complements thereof representative of said line conditions in said first and second registers respectively and for advancing stored indications therein, means responsive to the presence of consecutive indications of like conditions for each of said lines for forming in said first and second registers respectively first and second indications of the persistence of a signal or no-signal condition for each of said lines for consecutive ones of said command signals and for advancing said persistence indications to said first and second output positions respectively, and means responsive to each of consecutive ones of said first and second persistence indications for enabling an output from only said second or first output position respectively for consecutive ones of said lines.