Patent US3680048A successfully refreshed from Google Patents.
US3680048A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Core drive and biasing system
Assignee: TDK Corp
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Filing: 1970-03-04
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Granted: 1972-07-25
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Expires: 1990-03-04
Abstract
Abstract A read/write drive circuit for a circuit having a driver and a plurality of read/write circuit units connected in parallel thereto, wherein when one desired circuit unit is driven with a potential of one polarity, a potential of the opposite polarity is applied to other circuit units, thereby preventing a flow of current through the other circuit units and through an inadvertent ground path including stray capacitances. A higher speed operation is feasible because no charging current flows through the other circuit units that are not driven.
Inventors
- 👤 Joichiro Ezaki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 19:28
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/51; H03K17/56; H03K17/60; H03K17/66; H03K17/661; H03K17/662; G; G11; G11C; G11C11/00; G11C11/02; G11C11/06; G11C11/06007; H03K17/04; H03K17/041; H03K17/04113
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
194 words
A read and write drive circuit system for a plurality of read and write drive circuits for a core memory, said plurality of read drive circuits including groups of diodes having their anodes connected together to respective read drive lines, said plurality of write drive circuits including groups of diodes having their cathodes connected together to respective write drive lines, voltage divider means having points connected to respective ones of said read and write drive lines, and selection means for selectively forward biasing one diode of one of said groups of diodes and reversely biasing the remainder of the diodes of the group, at least one of the divider points being maintained at a voltage level less than ground when a corresponding read line is energized and being maintained at a voltage level greater than ground when a corresponding write line is energized so that said forward biased diode carries current to the core memory while the remainder of the diodes of the selected group are actively back biased to prevent stray capacitance between the cathode of read diodes and ground and between the anode or write diodes and ground from being inadvertently charged.
Claim 2
Dependent Claim
194 words
A read and write drive circuit system for a plurality of read and write drive circuits for a core memory, said plurality of read drive circuits including groups of diodes having their anodes connected together to respective read drive lines, said plurality of write drive circuits including groups of diodes having their cathodes connected together to respective write drive lines, voltage divider means having points connected to respective ones of said read and write drive lines, and selection means for selectively forward biasing one diode of one of said groups of diodes and reversely biasing the remainder of the diodes of the group, at least one of the divider points being maintained at a voltage level less than ground when a corresponding read line is energized and being maintained at a voltage level greater than ground when a corresponding write line is energized so that said forward biased diode carries current to the core memory while the remainder of the diodes of the selected group are actively back biased to prevent stray capacitance between the cathode of read diodes and ground and between the anode or write diodes and ground from being inadvertently charged.
Claim 3
Dependent Claim
132 words
A read and write drive circuit system as set forth in claim 1, wherein said selection means comprises a first driving transistor having collector and emitter terminals, and a second switching transistor having collector and emitter terminals, a source of positive voltage and a source of negative voltage, said voltage divider comprising a first load resistor connected between said source of positive voltage and said collector of said first driving transistor, and a second load resistor connected between the emitter of said second switching transistor and said source of negative voltage, said anode of the diode of said selected drive circuit being connected to the emitter of said first drive transistor and said cathode of said diode of said selected drive circuit being coupled to the collector of said second switching transistor.
Claim 4
Dependent Claim
64 words
A read and write drive circuit system as set forth in claim 2, wherein the magnitude of said positive and negative voltages aRe equal and the equivalent resistance between said emitter of said first driving transistor and said source of positive voltage is greater in value than the equivalent resistance between said collector of said second switching transistor and said source of negative potential.
Claim 5
Dependent Claim
173 words
A read and write drive circuit system as set forth in claim 3, comprising a read line and a corresponding write line and a switch terminal energized for pairs of corresponding read and write lines, a second driving transistor having emitter and collector terminals, said emitter of said first driving transistor and said collector of said second driving transistor connected to said read and write lines respectively, a first switching transistor having emitter and collector terminals, a third load resistor connected between the emitter of said second driving transistor and said source of negative voltage, a fourth load resistor connected between said collector of said first switching transistor and said source of positive voltage, said collector of said second switching transistor and said emitter of said first switching transistor connected together and to said switch terminal, and a write diode having an anode and a cathode, said anode of said write diode coupled to said switch terminal and said cathode of said write diode connected to said collector of said second driving transistor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-07-25 | 1976-01-24 | 1976-07-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-07-25 | 1980-01-24 | 1980-07-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-07-25 | 1984-01-24 | 1984-07-25 | $7700.00 | Window Closed / Lapsed |