Multivibrator circuits employing or-nor gates

Claim 2

An astable multivibrator comprising: a semiconductor integrated circuit ''''or-nor'''' gate, said ''''ornor'''' gate comprising a single stage, emitter-coupled-logic gate circuit including a pair of transistor means for respectively producing ''''or'''' and ''''nor'''' outputs, wherein the emitters of said transistor means are coupled together, said gate providing a non-inverted ''''or'''' output in response to an input applied to one input terminal of said gate, feedback means coupled between the non-inverted ''''or'''' output of said gate and the input terminal of the same gate, said feedback means including a timing capacitor serially coupled between said ''''or'''' output and said one input terminal, and a charging means for said capacitor coupled between the ''''nor'''' output of said gate and said one input terminal.

Claim 3

The apparatus according to claim 1 wherein said charging means for said capacitor comprises a resistance coupling the ''''nor'''' output of said gate to said one input terminal.

Claim 4

The apparatus according to claim 1 further including a disabling-enabling circuit for said apparatus comprising a second semiconductor integrated circuit gate for receiving a disabling-enabling input and for producing an output in response thereto, and means coupling the output of said second gate to the ''''nor'''' output of the first mentioned gage for selectively maintaining said ''''nor'''' output of said first mentioned gate at a predetermined voltage level, as well as for selectively releasing said ''''nor'''' output of said first mentioned gate for normal astable multivibrator operation.

Claim 5

The apparatus according to claim 3 wherein said means coupling an output of said second gate to the ''''nor'''' output of the first mentioned gate comprises a voltage divider disposed between positive and negative voltage points and having a first tap coupled to the said output of said second gate, and diode means coupling the ''''nor'''' output of the first mentioned gate to a more positive voltage tap on said voltage divider, said diode having its anode coupled to the last mentioned tap.

Claim 6

The circuit according to claim 3 wherein said predetermined voltage level is higher than the highest level normally provided at said ''''nor'''' output in the absence of said second gate by the highest voltage normally present across said timing capacitor.

Claim 7

The apparatus according to claim 3 wherein boTh said gates are provided as portions of the same semiconductor integrated circuit structure.

Claim 8

The multivibrator according to claim 1 wherein said ''''or-nor'''' gate includes a second input terminal, said second input terminal being connected to a bias voltage point.

Claim 9

An astable multivibrator circuit comprising: a gate circuit having input means and characterized by first and second states determined according to whether an input applied at said input means exceeds a predetermined input level, said gate producing inverted and non-inverted outputs, said inverted output residing above said input level in one state of said gate circuit and residing below said input level in the other state of said gate circuit, said gate circuit comprising a transistor stage utilizing emitter-coupled logic, said stage including a pair of transistors having their emitter terminals interconnected, and means coupling the collector of one of said transistors to provide the inverted output of said gate circuit as well as means coupling the collector of the second of said transistors to provide the non-inverted output of said gate circuit, a timing capacitor coupling said non-inverted output to said input means, and a resistance coupling said inverted output to said input means, said resistance providing charging means for said capacitor.

Claim 10

An astable multivibrator circuit comprising: a gate circuit having input means and characterized by first and second states determined according to whether an input applied at said input means exceeds a predetermined input level, said gate producing inverted and non-inverted outputs, said inverted output residing above said input level in one state of said gate circuit and residing below said input level in the other state of said gate circuit, said gate circuit comprising a transistor stage utilizing emitter-coupled logic, said stage including a pair of transistors having their emitter terminals interconnected, and means coupling the collector of one of said transistors to provide the inverted output of said gate circuit as well as means coupling the collector of the second of said transistors to provide the non-inverted output of said gate circuit, a timing capacitor coupling said non-inverted output to said input means, and a resistance coupling said inverted output to said input means, said resistance providing charging means for said capacitor.

Claim 11

The apparatus according to claim 8 wherein said means coupling the output of said one of said transistors to provide said inverted output comprises a first emitter-follower transistor and wherein the means coupling the collector of the second of said transistors to provide said non-inverted output comprises a second emitter-follower transistor, said input means comprising the base terminal of one of said pair of transistors.

Claim 12

The apparatus according to claim 8 wherein said transistors forming said gate circuit are provided within a common semiconductor integrated circuit structure.

Claim 13

An astable multivibrator circuit comprising: a gate circuit having input means and characterized by first and second states determined according to whether an input applied at said input means exceeds a predetermined input level, said gate producing inverted and non-inverted outputs, said inverted output residing above said input level in one state of said gate circuit and residing below said input level in the other state of said gate circuit, a timing capacitor coupling said non-inverted output to said input means, a resistance coupling said inverted output to said input means, said resistance providing charging means for said capacitor, and a disabling-enabling circuit comprising a second gate circuit for receiving a disabling-enabling input and for producing an output in response thereto, and means coupling the output of said second gate circuit to the inverted output of the first mentioned gate circuit for selectively maintaining said inverted output of said first mentioned gate circuit at a predetermined voltage level, as well as for selectively releasing said inverted output of said first mentioned gate circuit for normal astable multivibrator operation.

Claim 14

An astable multivibrator circuit comprising: a gate circuit having input means and characterized by first and second states determined according to whether an input applied at said input means exceeds a predetermined input level, said gate producing inverted and non-inverted outputs, said inverted output residing above said input level in one state of said gate circuit and residing below said input level in the other state of said gate circuit, a timing capacitor coupling said non-inverted output to said input means, a resistance coupling said inverted output to said input means, said resistance providing charging means for said capacitor, and a disabling-enabling circuit comprising a second gate circuit for receiving a disabling-enabling input and for producing an output in response thereto, and means coupling the output of said second gate circuit to the inverted output of the first mentioned gate circuit for selectively maintaining said inverted output of said first mentioned gate circuit at a predetermined voltage level, as well as for selectively releasing said inverted output of said first mentioned gate circuit for normal astable multivibrator operation.

Claim 15

The apparatus according to claim 4 wherein said means coupling an output of said second gate circuit to the inverted output of the first mentioned gate comprises a voltage divider disposed between positive and negative voltage points and having a first tap coupled to the said output of said second gate circuit, and diode means coupling the inverted output of the first mentioned gate circuit to a more positive voltage tap on said voltage divider, said diode means having an anode coupled to the last mentioned tap.

Claim 16

The circuit according to claim 4 wherein said predetermined voltage level is higher than the highest level normally provided at said inverted output in the absence of said second gate circuit by the highest voltage normally present across said timing capacitor.