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US3679915A
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Polarity hold latch with common data input-output terminal
Assignee: International Business Machines Corp
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Filing: 1971-03-04
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Granted: 1972-07-25
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Expires: 1991-03-04
Abstract
Abstract A logical circuit couples the in-phase output terminal of a polarity hold latch to the data input terminal of the latch to provide a common data input-output terminal. This is particularly useful in heavily integrated monolithically fabricated circuits where the amount of logical function that can be achieved is usually limited by the number of input-output pin connections that are available rather than the number of transistor circuits which are formed on a single semiconductor chip. However, the improved latch is also useful in reducing the number of inputoutput terminals in printed circuit cards for densely packaged electronic circuits since they also encounter pin limitations rather than electronic component limitations Gating means external to the semiconductor chip (or card) and in some instances gating of the logic circuit determine the time intervals when good input data and good output data exist on the common input-output terminals. In some instances, output data can be made available sooner than otherwise possible by careful use of the input data itself as good output data during the set time of the latch; i.e. the input signal to the latch is available sooner than its output and with the common input-output terminal its input signal can be used as an output signal before the latch output becomes available-an input to output signal delay of zero.
Inventors
- 👤 Ronald J Kriger
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 16:41
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/027; H03K3/037
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
174 words
In combination with a polarity hold latch having a data input line receiving signals at one or the other of two levels, an output line, a set-reset line, and means effective when a first signal level is applied to the setreset line for producing on he output line the same signal level as exists on the data input line and effective when a second signal level is applied to the set-reset line to maintain said the signal level on the output line irrespective of signal level changes on the data input line, a logical circuit providing the latch with a common data inputoutput line comprising one input connected directly to said output line, an output connected directly to said data input line, a second input connected directly to said set-reset line, and logical means effective when the second signal level is applied to the set-reset line for applying to said logical circuit output the signal level that exists on the latch output line to selectively provide latch output signals on the data input line.
Claim 2
Dependent Claim
174 words
In combination with a polarity hold latch having a data input line receiving signals at one or the other of two levels, an output line, a set-reset line, and means effective when a first signal level is applied to the setreset line for producing on he output line the same signal level as exists on the data input line and effective when a second signal level is applied to the set-reset line to maintain said the signal level on the output line irrespective of signal level changes on the data input line, a logical circuit providing the latch with a common data inputoutput line comprising one input connected directly to said output line, an output connected directly to said data input line, a second input connected directly to said set-reset line, and logical means effective when the second signal level is applied to the set-reset line for applying to said logical circuit output the signal level that exists on the latch output line to selectively provide latch output signals on the data input line.
Claim 3
Dependent Claim
36 words
The combination set forth in claim 1 carried by a single mounting structure having data and control signal pins for connecting the latch to other circuits, a common data input-output pin being provided for the latch.
Claim 4
Dependent Claim
63 words
The combination set forth in claim 2 wherein the polarity hold latch means includes a direct connection between the set-reset line and a reset input, and a signal delaying and inverting means between the set-reset line and a set input and effective to assure error free operation of the latch when said first and second signal levels are applied to the set-reset line.
Claim 5
Dependent Claim
30 words
The combination set forth in claim 2 together with means external to the mounting structure for selectively gating data input and output signals to and from the common input-output pin.
Claim 6
Dependent Claim
39 words
The combination set forth in claim 1 monolithically fabricated upon a single semiconductor chip and having a common data input-output pin connected to the data input line for coupling input and output data signals to and from the latch.
Claim 7
Dependent Claim
162 words
In combination with a polarity hold latch having a data input line receiving signals at one or the other of two levels, an output line, a set-reset line, and means effective when a first signal level is applied to the set-reset line for producing on the output line the same signal level as exists on the data input line and effective when a second signal level is applied to the set-reset line to maintain said same signal level on the output line irrespective of signal level changes on the data input line, a logical circuit comprising one input connected to said output line, an output connected to said data input line, a control input line, and logical means effective when a selected one of two signal levels is applied to the control input line for applying to said logical circuit output the signal level that exists on the latch output line to selectively provide latch output signals on the data input line.
Claim 8
Dependent Claim
162 words
In combination with a polarity hold latch having a data input line receiving signals at one or the other of two levels, an output line, a set-reset line, and means effective when a first signal level is applied to the set-reset line for producing on the output line the same signal level as exists on the data input line and effective when a second signal level is applied to the set-reset line to maintain said same signal level on the output line irrespective of signal level changes on the data input line, a logical circuit comprising one input connected to said output line, an output connected to said data input line, a control input line, and logical means effective when a selected one of two signal levels is applied to the control input line for applying to said logical circuit output the signal level that exists on the latch output line to selectively provide latch output signals on the data input line.
Claim 9
Dependent Claim
36 words
The combination set forth in claim 6 carried by a single mounting structure having data and control signal pins for connecting the latch to other circuits, a common data input-output pin being provided for the latch.
Claim 10
Dependent Claim
67 words
The combination set forth in claim 7 wherein the polarity hold latch means includes a direct connection between the set-reset line and a reset input, and a signal delaying and inverting means between tHe set-reset line and a set input and effective to assure error free operation of the latch when the signal level applied to the set-reset line changes from said first to said second level.
Claim 11
Dependent Claim
30 words
The combination set forth in claim 7 together with means external to the mounting structuRe for selectively gating data input and output signals to and from the common input-output pin.
Claim 12
Dependent Claim
39 words
The combination set forth in claim 6 monolithically fabricated upon a single semiconductor chip and having a common data input-output pin connected to the data input line for coupling input and output data signals to and from the latch.
Claim 13
Dependent Claim
221 words
An electronic circuit carried by a single packaging structure having a minimum number of data input and output pins for electrical connection with circuits on other structures comprising, a plurality of polarity hold latches mounted on the structure, each latch having a data input line receiving signals at one or the other of two levels, an output line, a set-reset line, and means effective when a first signal level is applied to the set-reset line for producing on the output line the same signal level as exists on the data input line and effective when a second signal level is applied to the set-reset line to maintain said same signal level on the output line irrespective of signal level changes on the data input line, and a plurality of logical circuits, one for each latch, and each comprising one input connected to its respective latch output line, an output connected to its respective latch data input line, a control input line, and logical means effective when a selected one of two signal levels is applied to its control input line for applying to its respective logical circuit output the signal level that exists on its respective latch output line to selectively provide latch output signals on its latch data input line thereby providing a common data input-output connection for each latch.
Claim 14
Dependent Claim
221 words
An electronic circuit carried by a single packaging structure having a minimum number of data input and output pins for electrical connection with circuits on other structures comprising, a plurality of polarity hold latches mounted on the structure, each latch having a data input line receiving signals at one or the other of two levels, an output line, a set-reset line, and means effective when a first signal level is applied to the set-reset line for producing on the output line the same signal level as exists on the data input line and effective when a second signal level is applied to the set-reset line to maintain said same signal level on the output line irrespective of signal level changes on the data input line, and a plurality of logical circuits, one for each latch, and each comprising one input connected to its respective latch output line, an output connected to its respective latch data input line, a control input line, and logical means effective when a selected one of two signal levels is applied to its control input line for applying to its respective logical circuit output the signal level that exists on its respective latch output line to selectively provide latch output signals on its latch data input line thereby providing a common data input-output connection for each latch.
Claim 15
Dependent Claim
80 words
The combination set forth in claim 11 wherein each polarity hold latch means includes a direct connection between the set-reset line and a respective reset input, a direct connection between the set-reset line and the control input line associated with its latch, and a signal delaying and inverting means between the set-reset line and a set input and effective to assure error free operation of the latch when said first and second signal levels are applied to the set-reset line.
Claim 16
Dependent Claim
42 words
The combination set forth in claim 11 together with a common input-output pin connected to each latch data input line, and means external to the packaging structure for selectively gating data input and output signals to and from each common input-output pin.
Claim 17
Dependent Claim
53 words
The combination set forth in claim 11 wherein the packaging structure is a single semiconductor chip, wherein the electronic circuit is monolithically fabricated upon said chip, and wherein a respective common data input-output pin is connected to each data input line for coupling input and output data signals to and from each latch.
Claim 18
Dependent Claim
194 words
A polarity hold latch monolithically fabricated on a single semiconductor chip and having a common data input-output pin, said latch comprising a data input line connected to said pin for receiving signals at one or the other of two levels, a latch output line, a set-reset line, first logical circuit means effective when a first signal level is applied to the set-reset line for producing on the latch output line the same signal level as exists on the data input line and effective when a second signal level is applied to the set-reset line to maintain said same signal level on the output line irrespective of signal level changes on the data input line, second logical circuit means having an input connected to the output line and an output connected to said pin and effective to produce at its output the same signal level as that on the latch output line, said first logical circuit means including a signal delaying and inverting means between the set-reset line and a set input and effective to assure error free operation of the latch when said first and second signal levels are applied to the set-reset line.
Claim 19
Dependent Claim
194 words
A polarity hold latch monolithically fabricated on a single semiconductor chip and having a common data input-output pin, said latch comprising a data input line connected to said pin for receiving signals at one or the other of two levels, a latch output line, a set-reset line, first logical circuit means effective when a first signal level is applied to the set-reset line for producing on the latch output line the same signal level as exists on the data input line and effective when a second signal level is applied to the set-reset line to maintain said same signal level on the output line irrespective of signal level changes on the data input line, second logical circuit means having an input connected to the output line and an output connected to said pin and effective to produce at its output the same signal level as that on the latch output line, said first logical circuit means including a signal delaying and inverting means between the set-reset line and a set input and effective to assure error free operation of the latch when said first and second signal levels are applied to the set-reset line.
Claim 20
Dependent Claim
29 words
The combination set forth in claim 15 together with means external to the chip for selectively gating data input and output signals to and from the common input-output pin.
References Cited (Backward Citations)
US3524080A
Cited
US3569842A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-07-25 | 1976-01-24 | 1976-07-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-07-25 | 1980-01-24 | 1980-07-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-07-25 | 1984-01-24 | 1984-07-25 | $7700.00 | Window Closed / Lapsed |