Regenerative circuit comprising complementary transistor pairs

Claim 2

In combination, first and second complementary transistor pairs, first circuit means operative for switching both transistors of said first pair substantially concurrently to a nonconducting state, network means including direct current paths for interconnecting said first and second transistor pairs such that said first pair is nonconducting when said second pair is conducting and vice versa, and triggering means including said first circuit means and said network means for switching said second pair to a transition state only after both transistors of said first pair have been switched to a nonconducting state.

Claim 3

The combination in accordance with claim 1, further comprising second circuit means operative for switching both transistors of said second pair substantially concurrently to a nonconducting state, and means including said interconnecting means for switching said first pair of transistors to a conducting state responsive to the switching of said second pair of transistors to a nonconducting state.

Claim 4

The combination in accordance with claim 1 wherein said first circuit means comprises clamping means connected to said first pair of transistors operative for biasing both transistors of said first pair nonconducting, and means for operating said clamping means.

Claim 5

In combination, first and second complementary transistor pairs, first circuit means operative for switching both transistors of said first pair substantially concurrently to a nonconducting state, said first circuit means comprising clamping means connected to said first pair of transistors operative for biasing both transistors of said first pair nonconducting, said clamping means comprising a complementary pair of clamping transistors respectively connected to the two transistors of said first pair, means for operating said clamping means comprising means for switching said pair of clamping transistors to a conducting state substantially concurrently, and means including direct current paths for interconnecting said first and second transistor pairs such that the switching of said second pair to a nonconducting state causes said second pair to switch to a conducting state.

Claim 6

In combination, first and second complementary transistor pairs, first circuit means operative for switching both transistors of said first pair substantially concurrently to a nonconducting state, said first circuit means comprising clamping means connected to said first pair of transistors operative for biasing both transistors of said first pair nonconducting, said clamping means comprising a complementary pair of clamping transistors respectively connected to the two transistors of said first pair, means for operating said clamping means comprising means for switching said pair of clamping transistors to a conducting state substantially concurrently, and means including direct current paths for interconnecting said first and second transistor pairs such that the switching of said second pair to a nonconducting state causes said second pair to switch to a conducting state.

Claim 7

The combination in accordance with claim 4 further comprising second circuit means operative for switching both transistors of said second pair substantially concurrently to a nonconducting state, and means including said interconnecting means for switching said first pair of transistors to a conducting state responsive to the switching of said second pair to a nonconducting state.

Claim 8

The combination in accordance with claim 5 further comprising means for operating said second circuit means in response to the switching of said second transistor pair from a nonconducting to a conducting state, whereby said second pair is returned to said nonconducting state.

Claim 9

The combination in accordance with claim 6 wherein said means for operating said second circuit means comprises timing circuit means for controlling the period of time said second pair is in said conducting state.

Claim 10

A regenerative switching circuit having first and second states including, first, second, third and fourth transistors, said first and third transistors comprising a first pair of complementary transistors which are conducting in said first state, And said second and fourth transistors comprising a second pair of complementary transistors which are conducting in said second state, means interconnecting said first and second transistor pairs such that said second pair is nonconducting when said first pair is conducting, and vice versa, said interconnecting means including a first direct current path interconnecting said first and fourth transistors and a second direct current path interconnecting said second and third transistors, first circuit means connected to said first pair operative for effecting transitions from said first state to said second state by switching both transistors of said first pair to a nonconducting condition substantially concurrently, and means including said first circuit means and said interconnecting means for switching said second pair to a transition state only after both transistors of said first pair have been switched to a nonconducting state.

Claim 11

A regenerative switching circuit having first and second states including, first, second, third and fourth transistors, said first and third transistors comprising a first pair of complementary transistors which are conducting in said first state, And said second and fourth transistors comprising a second pair of complementary transistors which are conducting in said second state, means interconnecting said first and second transistor pairs such that said second pair is nonconducting when said first pair is conducting, and vice versa, said interconnecting means including a first direct current path interconnecting said first and fourth transistors and a second direct current path interconnecting said second and third transistors, first circuit means connected to said first pair operative for effecting transitions from said first state to said second state by switching both transistors of said first pair to a nonconducting condition substantially concurrently, and means including said first circuit means and said interconnecting means for switching said second pair to a transition state only after both transistors of said first pair have been switched to a nonconducting state.

Claim 12

A regenerative switching circuit in accordance with claim 8 wherein said first circuit means comprises clamping means connected to said first pair of transistors operative for biasing both transistors of said first pair nonconducting, and means for operating said clamping means.

Claim 13

A regenerative switching circuit in accordance with claim 8 further comprising output means connected to at least one of said direct current paths and impedance means connected in said one of said direct current paths, said one of said direct current paths comprising means for interconnecting the collectors of said first and fourth transistors, whereby the voltage at said output means is controlled by said impedance means.

Claim 14

A regenerative switching circuit having first and second states including, first, second, third and fourth transistors, said first and third transistors comprising a first pair of complementary transistors which are conducting in said first state, and said second and fourth transistors comprising a second pair of complementary transistors which are conducting in said second state, means interconnecting said first and second transistor pairs such that said second pair is nonconducting when said first pair is conducting, and vice versa, said interconnecting means including a first direct current path interconnecting said first and fourth transistors and a second direct current path interconnecting said second and third transistors, first circuit means connected to said first pair operative for effecting transitions from said first state to said second state by switching both transistors of said first pair to a nonconducting condition substantially concurrently, said first circuit means comprising clamping means connected to said first pair of transistors operative for biasing both transistors of said first pair nonconducting, and means for operating said clamping means, said clamping means comprising a complementary pair of clamping transistors respectively connected to said first and third transistors, and said operating means comprising switching means for interconnecting the bases of said pair of clamping transistors such that activation of said switching means causes said pair of clamping transistors to switch to a conducting state substantially concurrently.

Claim 15

A regenerative switching circuit having first and second states including, first, second, third and fourth transistors, said first and third transistors comprising a first pair of complementary transistors which are conducting in said first state, and said second and fourth transistors comprising a second pair of complementary transistors which are conducting in said second state, means interconnecting said first and second transistor pairs such that said second pair is nonconducting when said first pair is conducting, and vice versa, said interconnecting means including a first direct current path interconnecting said first and fourth transistors and a second direct current path interconnecting said second and third transistors, first circuit means connected to said first pair operative for effecting transitions from said first state to said second state by switching both transistors of said first pair to a nonconducting condition substantially concurrently, said first circuit means comprising clamping means connected to said first pair of transistors operative for biasing both transistors of said first pair nonconducting, and means for operating said clamping means, said clamping means comprising a complementary pair of clamping transistors respectively connected to said first and third transistors, and said operating means comprising switching means for interconnecting the bases of said pair of clamping transistors such that activation of said switching means causes said pair of clamping transistors to switch to a conducting state substantially concurrently.