Binary flip-flop employing insulated gate field effect transistors and suitable for cascaded frequency divider operation

Claim 2

A binary flip-flop of the type functioning to provide an output signal at one half the frequency of an input signal, wherein the input signal includes a first input signal, and a second input signal which is the inverse of said first input signal, and said first signal is a bi-level input pulse train comprising a series of repetitive cycles and each of said cycles includes a first time period corresponding to a first of said levels and a second time period corresponding to a second of said levels, the improvement comprising: a memory means having a first output signal for indicating during one time period the level of said first input signal during the immediately preceeding time period and for maintaining said indication for an additional time period; and an output transfer means responsive to said first input signal and to said second input signal and to said first output signal for generating a second output signal and a third output signal corresponding to one half the frequency of said first input signal and to said second input signal respectively, and said second output signal being a bi-level series of repetitive cycles and said third output signal being the inverse of said second output signal.

Claim 3

The invention as recited in claim 1, wherein said memory means comprises: first means for preventing during said first time period a reversal of said output level of said first output signal coincident with a reversal of said output level of said second output signal; and second means for reversing during said second time period said output level of said first output signal.

Claim 4

The invention as recited in claim 1, wherein said output transfer means comprises: first means for causing during said first time period a reversal of said output level of said second output signal; and second means for maintaining during said second time period said level of said second output signal established during said first time period.

Claim 5

The invention as recited in claim 2, wherein said memory means is fabricated with field effect transistors and comprises: a source of potential having a first potential level and a second level of potential and said first level being more positive than said second level; a plurality of P-channel and N-channel field effect transistors and each having source, gate and drain electrodes; a first P-channel transistor having its source connected to said first potential level and having its gate connected to said first input signal; a first N-channel transistor having its source connected to said second potential level and having its gate connected to said first input signal; a second N-channel transistor having its source connected to said drain of said first N-channel transistor; a second P-channel transistor having its gate connected to a first junction with said gate electrode of said second N-channel transistor and having its source connected to said first potential level and having its drain connected to a second junction with said drain of said first P-channel transistor; a third P-channel transistor having its source connected to said second junction and having its drain connected to a third junction with said drain of said second N-channel transistor; a third N-channel transistor having its drain connected to said third junction and its gate connected to said gate of said third P-channel transistor and responsive to said second output signal; a fourth N-cHannel transistor having its drain connected to said source of said third N-channel transistor and having its source connected to said second level of potential and having its gate responsive to said second input signal; a fourth P-channel transistor having its source connected to said second junction and having its drain connected to said third junction and having its gate responsive to said second input signal; a fifth P-channel transistor having its source connected to said first potential level and having its gate connected to said third junction and having its drain connected to said first junction; a fifth N-channel transistor having its gate connected to said third junction and having its drain connected to said first junction and having its source connected to said first potential level whereby, said first junction is the output signal of said memory means.

Claim 6

The invention as recited in claim 3, wherein said output transfer means is fabricated with field effect transistors and comprises: a source of potential having a first potential level and a second level of potential and said first level being more positive than said second level; a plurality of P-channel and N-channel field effect transistors and each having source, gate and drain electrodes; a first P-channel transistor having its source connected to said first potential level and having its gate connected to said first output signal; a first N-channel transistor having its source connected to said second potential level and having its gate connected to said first input signal; a second N-channel transistor having its source connected to said drain of said first N-channel transistor and having its gate connected to said first output signal; a second P-channel transistor having its gate connected to a first junction with said gate electrode of said first N-channel transistor and having its source connected to said first potential level and having its drain connected to a second junction with said drain of said first P-channel transistor; a third P-channel transistor having its source connected to said second junction and having its drain connected to a third junction with said drain of said second N-channel transistor; a third N-channel transistor having its drain connected to said third junction and its gate connected to said gate of said third P-channel transistor and responsive to said third output signal; a fourth N-channel transistor having its drain connected to said source of said third N-channel transistor and having its source connected to said second level of potential and having its gate responsive to said second input signal; a fourth P-channel transistor having its source connected to said second junction and having its drain connected to said third junction and having its gate responsive to said second input signal; a fifth P-channel transistor having its source connected to said first potential level and having its gate connected to said third junction and having its drain connected to a fourth junction; a fifth N-channel transistor having its gate connected to said third junction and having its drain connected to said fourth junction and having its source connected to said first potential level whereby, said fourth junction is the third output signal of said output transfer means and said third junction provides said second output of said output transfer means.

Claim 7

A binary flip-flop of the type fabricated with field effect transistors and functioning to provide an output indicia at one half the frequency of an input signal indicia comprising: a source of potential having a first potential level and a second potential level and said first level being more positive than said second level; an input signal including a first input signal and a second input signal which is the inverse of said first input signal; a plurality of P-channel and N-channel field effEct transistors and each having source, gate and drain electrodes; a first N-channel transistor having its source connected to said second level and its drain connected to a first junction and its gate connected to a second junction; a first P-channel transistor having its drain connected to said first junction and having its gate connected to said second junction and having its source connected to said first level; a second N-channel transistor having its gate connected to said first junction and having its drain connected to said second junction and having its source connected to a third junction; a second P-channel transistor having its gate connected to a first junction and having its drain connected to said second junction and having its source connected to a fourth junction; a third P-channel transistor having its source connected to said fourth junction and having its drain connected to said second junction; a fourth P-channel transistor having its source connected to said first potential level and having its drain connected to said fourth junction and having its gate connected to a fifth junction; a fifth P-channel transistor having its source connected to said first potential level and having its drain connected to said fourth junction and having its gate responsive to said first input signal; a sixth P-channel transistor having its source connected to said fourth junction and having its drain connected to a sixth junction and having its gate connected to said gate of said third P-channel transistor and of said two last mentioned gates responsive to said second input signal; a seventh P-channel transistor having its source connected to said fourth junction and having its drain connected to said sixth junction and having its gate connected to said second junction; a third N-channel transistor having its drain connected to said third junction and having its source connected to said second potential level and having its gate responsive to said second input signal; a fourth N-channel transistor having its drain connected to said second junction and having its gate connected to said fifth junction; a fifth N-channel transistor having its drain connected to said source of said fourth N-channel transistor and having its source connected to said second potential level and having its gate responsive to said first input signal; a sixth N-channel transistor having its drain connected to said sixth junction and having its gate connected to said fifth junction; a seventh N-channel transistor having its source connected to said second potential source and having its drain connected to said source of said sixth N-channel transistor and having its gate responsive to said first input signal; an eighth N-channel transistor having its drain connected to said sixth junction and having its source connected to said third junction and having its gate connected to said second junction; an eighth P-channel transistor having its source connected to said first potential level and having its gate connected to said sixth junction and having its drain connected to said fifth junction; a ninth N-channel transistor having its gate connected to said sixth junction and having its drain connected to said fifth junction and having its source connected to said second potential level; said fifth junction being a first output signal; said second junction being a second output signal; and said first junction being a third output signal.

Claim 8

A binary flip-flop of the type fabricated with field effect transistors and functioning to provide an output indicia at one half the frequency of an input signal indicia comprising: a source of potential having a first potential level and a second potential level and said first level being more positive than said second level; an input signal including a first input signal and a second input signal which is the inverse of said first input signal; a plurality of P-channel and N-channel field effEct transistors and each having source, gate and drain electrodes; a first N-channel transistor having its source connected to said second level and its drain connected to a first junction and its gate connected to a second junction; a first P-channel transistor having its drain connected to said first junction and having its gate connected to said second junction and having its source connected to said first level; a second N-channel transistor having its gate connected to said first junction and having its drain connected to said second junction and having its source connected to a third junction; a second P-channel transistor having its gate connected to a first junction and having its drain connected to said second junction and having its source connected to a fourth junction; a third P-channel transistor having its source connected to said fourth junction and having its drain connected to said second junction; a fourth P-channel transistor having its source connected to said first potential level and having its drain connected to said fourth junction and having its gate connected to a fifth junction; a fifth P-channel transistor having its source connected to said first potential level and having its drain connected to said fourth junction and having its gate responsive to said first input signal; a sixth P-channel transistor having its source connected to said fourth junction and having its drain connected to a sixth junction and having its gate connected to said gate of said third P-channel transistor and of said two last mentioned gates responsive to said second input signal; a seventh P-channel transistor having its source connected to said fourth junction and having its drain connected to said sixth junction and having its gate connected to said second junction; a third N-channel transistor having its drain connected to said third junction and having its source connected to said second potential level and having its gate responsive to said second input signal; a fourth N-channel transistor having its drain connected to said second junction and having its gate connected to said fifth junction; a fifth N-channel transistor having its drain connected to said source of said fourth N-channel transistor and having its source connected to said second potential level and having its gate responsive to said first input signal; a sixth N-channel transistor having its drain connected to said sixth junction and having its gate connected to said fifth junction; a seventh N-channel transistor having its source connected to said second potential source and having its drain connected to said source of said sixth N-channel transistor and having its gate responsive to said first input signal; an eighth N-channel transistor having its drain connected to said sixth junction and having its source connected to said third junction and having its gate connected to said second junction; an eighth P-channel transistor having its source connected to said first potential level and having its gate connected to said sixth junction and having its drain connected to said fifth junction; a ninth N-channel transistor having its gate connected to said sixth junction and having its drain connected to said fifth junction and having its source connected to said second potential level; said fifth junction being a first output signal; said second junction being a second output signal; and said first junction being a third output signal.

Claim 9

A multistage divider wherein each stage comprises a binary flip-flop according to claim 6, wherein said first input signal and said second input signal of the second stage comprises the second and third output signals from the first stage.

Claim 10

A binary flip-flop comprising first, second, third and fourth AND gates, each of said AND gates having two input terminals and an output terminal; first and secoNd NOR gates, each of said NOR gates having two input terminals and an output terminal; first and second inverters, each of said inverters having an input terminal and an output terminal; means for connecting the output terminals of said first and second AND gates respectively to the input terminals of said first NOR gate; means for connecting the output terminal of said first NOR gate to the input terminal of said first inverter; means for connecting the output terminal of said first inverter to a first input terminal of said first AND gate; means for connecting the output terminals of said third and fourth AND gates respectively to the input terminals of said second NOR gate; means for connecting the output terminal of said second NOR gate to the input terminal of said second inverter; means for interconnecting first input terminals of said second and fourth AND gates; means for interconnecting a second input terminal of said first and third AND gates; means for connecting the first input terminal of said third AND gate to the output terminal of said first NOR gate; and means for connecting the output terminal of said second inverter to the second input terminals of said second and fourth AND gates, whereby the binary inputs to said flip-flop are applied at said two interconnecting means, with the outputs of said flip-flop being available at the input and output terminals of said first inverter.

Claim 11

A binary flip-flop comprising first, second, third and fourth AND gates, each of said AND gates having two input terminals and an output terminal; first and secoNd NOR gates, each of said NOR gates having two input terminals and an output terminal; first and second inverters, each of said inverters having an input terminal and an output terminal; means for connecting the output terminals of said first and second AND gates respectively to the input terminals of said first NOR gate; means for connecting the output terminal of said first NOR gate to the input terminal of said first inverter; means for connecting the output terminal of said first inverter to a first input terminal of said first AND gate; means for connecting the output terminals of said third and fourth AND gates respectively to the input terminals of said second NOR gate; means for connecting the output terminal of said second NOR gate to the input terminal of said second inverter; means for interconnecting first input terminals of said second and fourth AND gates; means for interconnecting a second input terminal of said first and third AND gates; means for connecting the first input terminal of said third AND gate to the output terminal of said first NOR gate; and means for connecting the output terminal of said second inverter to the second input terminals of said second and fourth AND gates, whereby the binary inputs to said flip-flop are applied at said two interconnecting means, with the outputs of said flip-flop being available at the input and output terminals of said first inverter.

Claim 12

A binary flip-flop of the type functioning to provide an output signal at one half the frequency of an input signal, wherein the input signal includes a first input waveform and a second input waveform which is the inverse of said first input waveform, and said first input waveform is a bi-level input pulse train comprising a series of repetitive cycles and each of said cycles includes a first time period corresponding to a first of said levels and a second time period corresponding to a second of said levels, the improvement comprising: a memory means having a first output signal for indicating during one time period the level of said input waveform during the immediately preceeding time period, and for maintaining said indication for an additional time period; an output transfer means having a second output signal corresponding to one half the frequency of said first input waveform and having a third waveform which is the inverse of the waveform of said second output signal; said memory means responsive to said first input waveform and to said second input waveform and to said first output signal and to said second output signal, for preventing the reversal of the output level of said first output signal coincident with the reversal of the output level of said second output signal during said first time period, and for generating a first output signal having an output level equal to said third output waveform during said second time period; and said output transfer means responsive to said first input waveform and to said second input waveform and to said first output signal and to said third output waveform for forcing during said first time period said third output waveform to change output level, and for maintaining during said second time period said output level, established during said first time period; whereby, said first output signal and said third output change levels asynchronously.

Claim 13

A binary flip-flop of the type functioning to provide an output signal at one half the frequency of an input signal, wherein the input signal includes a first input waveform and a second input waveform which is the inverse of said first input waveform, and said first input waveform is a bi-level input pulse train comprising a series of repetitive cycles and each of said cycles includes a first time period corresponding to a first of said levels and a second time period corresponding to a second of said levels, the improvement comprising: a memory means having a first output signal for indicating during one time period the level of said input waveform during the immediately preceeding time period, and for maintaining said indication for an additional time period; an output transfer means having a second output signal corresponding to one half the frequency of said first input waveform and having a third waveform which is the inverse of the waveform of said second output signal; said memory means responsive to said first input waveform and to said second input waveform and to said first output signal and to said second output signal, for preventing the reversal of the output level of said first output signal coincident with the reversal of the output level of said second output signal during said first time period, and for generating a first output signal having an output level equal to said third output waveform during said second time period; and said output transfer means responsive to said first input waveform and to said second input waveform and to said first output signal and to said third output waveform for forcing during said first time period said third output waveform to change output level, and for maintaining during said second time period said output level, established during said first time period; whereby, said first output signal and said third output change levels asynchronously.

Claim 14

The invention as recited in claim 9, wherein said memory means further comprises: first means responsive to said second output signal and to said second input waveform for preventing during said first time period the reversal of the output level of said first output signal coincident with the reversal of the output level of said second output signal, and for generating during said second time period a first output signal of the same output level as said third output signal; second means responsive to said first output signal and to said first input waveform for maintaIning in said first time period the output level of said first output signal during a reversal in levels in said second output waveform, and for allowing in said second time period said output level of said first output signal to equal the output level of said third output signal; and first summing means including polarity reversal means for developing said output signal.

Claim 15

The invention as recited in claim 9, wherein said output transfer means further comprises: first means responsive to said third output signal and said second input waveform for allowing during said first time period a reversal of said output level of said third output signal; and for maintaining during said second time period the output level of said third output signal established during said first time period; second means responsive to said first output signal and said first input waveform, for causing during said first time period a reversal of said output level of said third output signal as indicated by said first output signal, and for inhibiting during said second time period, a changing of said output level of said third output signal in response to said first output signal; summing means for developing said second output signal; and polarity reversal means for developing said third output signal.

Claim 16

A multistage divider wherein each stage comprises a binary flip-flop according to claim 9; wherein said first input signal and said second input signal of the second stage comprises the second and third output signals from the first stage.