US3679879A
Expired / Lapsed
US
⏱️ 0.0 years remaining
System for generating speed pattern for speed control of moving body
Assignee: Hitachi Ltd
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Filing: 1969-12-18
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Granted: 1972-07-25
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Expires: 1989-12-18
Abstract
Abstract A system for generating a speed pattern for the speed control of a moving body comprising a first register which is preset with the total variation of time including the time required when the speed of the moving body ranging from the initial speed to the final speed is controlled by a predetermined rate of speed change, a coefficient multiplier for computing a very small variation of time during the control of the speed of the moving body by said rate of speed change, a second register to which the result of addition of the output from said coefficient multiplier and the content of said first register is supplied each time a variation of speed occurs during said very small variation of time, and an amplifier having a very great gain for comparing a train of overflow pulses from said second register with a train of pulses, each one thereof representing one unit of the distance, and delivering an output representing the said variation of speed.
Inventors
- 👤 Susumu Seki
- 👤 Makoto Noumi
- 👤 Tadashi Takaoka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 10:07
CPC Classifications
B; B66; B66B; B66B1/00; B66B1/24; B66B1/28; B66B1/285; B60; B60K; B60K31/00; B60K31/02; B60T; B60T7/00; B60T7/12; G; G06; G06F; G06F7/00; G06F7/60; G06F7/64; G06F7/66
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
189 words
A system for generating a speed pattern for the speed control of a moving body comprising a first register which is preset at a first input thereof with the total variation of time including the time required when the speed of the moving body ranging from the initial speed to the final speed is controlled by a predetermined rate of speed change, a coefficient multiplier connected to a second input of said first register for computing a very small variation of time during the control of the speed of the moving body by said rate of speed change and for delivering said variation to said first register, a second register to which the result of addition of the output of said coefficient multiplier and the content of said first register is supplied each time a variation of speed occurs during said very small variation of time, and means, connected to said second register for comparing a train of overflow pulses from said second register with a first train of pulses, each one thereof representing one unit of the distance, and delivering an output representing the said variation of speed.
Claim 2
Independent Claim
189 words
A system for generating a speed pattern for the speed control of a moving body comprising a first register which is preset at a first input thereof with the total variation of time including the time required when the speed of the moving body ranging from the initial speed to the final speed is controlled by a predetermined rate of speed change, a coefficient multiplier connected to a second input of said first register for computing a very small variation of time during the control of the speed of the moving body by said rate of speed change and for delivering said variation to said first register, a second register to which the result of addition of the output of said coefficient multiplier and the content of said first register is supplied each time a variation of speed occurs during said very small variation of time, and means, connected to said second register for comparing a train of overflow pulses from said second register with a first train of pulses, each one thereof representing one unit of the distance, and delivering an output representing the said variation of speed.
Claim 3
Dependent Claim
62 words
A system for generating a speed pattern as claimed in claim 1, in which said total variation of time preset in said first register includes the time required when the speed of the moving body ranging from the initial speed to the final speed is controlled by the predetermined rate of speed change and the free running time of the moving body.
Claim 4
Dependent Claim
56 words
A system for generating a speed pattern as claimed in claim 1, in which said coefficient multiplier comprises a register which is preset with the number of pulses proportional to a predetermined coefficient, and another register to which the coefficient is supplied each time the variation of speed occurs during said very small variation of time.
Claim 5
Dependent Claim
87 words
A system for generating a speed pattern as claimed in claim 1, in which said comparing means comprises a third register to which the overflow pulses from said second register and the first pulses, each one of which represents one unit of the distance, are supplied in each predetermined computing cycle, the content of said third register representing the difference of the signals applied thereto, and means, responsive to said third register, for discriminating whether the content of saId third register is larger than a predetermined value.
Claim 6
Dependent Claim
56 words
A system according to claim 4, wherein said discriminating means includes a first adder circuit having one input thereof connected to the output of said third register and having another input thereof connected to the output of a fourth register, the input of said fourth register being connected to the output of said first adder circuit.
Claim 7
Dependent Claim
96 words
A system according to claim 5, wherein said discriminating means further includes a second adder circuit having one input thereof gateably connected to the output of said first adder circuit, and a fifth register connected to a second input of said second adder circuit, the output of said fifth register being connected to one input thereof and having another input thereof connected to receive a predetermined number of pulses and further including a clock pulse generator for controlling the connection of the output of said first adder circuit to one input of said second adder circuit.
Claim 8
Dependent Claim
79 words
A system according to claim 6, further including a first gate circuit connected between the output of said first adder circuit and one input of said second adder circuit and having its control input connected to the output of said clock pulse generator, and further including an AND gate connected to receive the output of said clock pulse generator and the output of said second adder circuit, said AND gate delivering said output representative of said variation of speed.
Claim 9
Dependent Claim
40 words
A system according to claim 7, further including a second gate circuit connected between the output of said first register and the input of said second register, and having its control input connected to the output of said AND gate.
Claim 10
Dependent Claim
49 words
A system according to claim 8, wherein said coefficient multiplier comprises a register which is preset with a number of pulses proportional to a predetermined coefficient and another register, to which the coefficient is supplied each time the variation of speed occurs during said very small variation of time.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-07-25 | 1976-01-24 | 1976-07-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-07-25 | 1980-01-24 | 1980-07-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-07-25 | 1984-01-24 | 1984-07-25 | $7700.00 | Window Closed / Lapsed |