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US3148273A Expired / Lapsed US ⏱️ 0.0 years remaining

Incremental differential analyzer

Assignee: Electronic Associates Inc
•
Filing: 1961-01-03
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Granted: 1964-09-08
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Expires: 1981-01-03
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Abstract

No abstract record available.

Inventors

  • 👤 Thomas D Truitt
  • 👤 Lee P Neuwirth

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-25 21:24
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/60; G06F7/64; G06F7/68

Claims Analysis

Total Claims: 2
Claim 1
Independent Claim 397 words
AN INCREMENTAL INTEGRATOR COMPRISING A FIRST BINARY COUNTER HAVING A PLURALITY OF STAGES, FIRST MEANS FOR INTRODUCING INTO ANY SELECTED ONE OF SAID PLURALITY OF STAGES A STREAM OF PULSES REPRESENTING VARIATIONS IN AN INDEPENDENT QUANTITY TO PRODUCE A PULSE OUTPUT FROM THE LEAST SIGNIFICANT BIT STAGE AT 1/2 OF THE PULSE RATE OF SAID INDEPENDENT QUANTITY, A PULSE OUTPUT FROM THE SECOND LEAST SIGNIFICANT BIT STAGE AT 1/4 OF THE PULSE RATE OF SAID INDEPENDENT QUANTITY ... A PULSE OUTPUT FROM THE MOST SIGNIFICANT BIT STAGE "N" AND 1/2N OF THE PULSE RATE OF SAID INDEPENDENT QUANTITY, A SECOND BINARY COUNTER HAVING AT LEAST THE SAME NUMBER OF STAGES AS SAID FIRST BINARY COUNTER, SECOND MEANS FOR INTRODUCING INTO ANY SELECTED ONE OF SAID PLURALITY OF STAGES OF SAID SECOND COUNTER A STREAM OF PULSES REPRESENTING VARIATIONS IN A DEPENDENT QUANTITY TO PRODUCE A CHANGE IN STATE OF DIFFERENT ONES OF SAID PLURALITY OF STAGES IN SAID SECOND COUNTER, A PLURALITY OF GATE CIRCUITS EACH CONNECTED TO ONE OF THE STAGES OF SAID FIRST COUNTER AND CONNECTED TO ONE OF THE STAGES IN THE SECOND COUNTER IN AN INVERSE RELATIONSHIP WITH THE LEAST SIGNIFICANT BIT STAGE OF SAID FIRST COUNTER AND THE MOST SIGNIFICANT BIT STAGE OF SAID SECOND COUNTER BEING CONNECTED TO A FIRST OF SAID GATE CIRCUITS, THE NEXT LEAST SIGNIFICANT BIT STAGE OF SAID FIRST COUNTER AND THE NEXT MOST SIGNIFICANT BIT STAGE OF THE SECOND COUNTER BEING CONNECTED TO A SECOND OF SAID GATE CIRCUITS ... THE MOST SIGNIFICANT BIT STAGE OF SAID FIRST COUNTER AND SAID LEAST SIGNIFICANT BIT STAGE OF SAID SECOND COUNTER BEING CONNECTED TO AN NTH OF SAID GATE CIRCUITS TO PASS OUTPUT PULSES UPON A PARTICULAR CHANGE OF STATE IN A STAGE OF SAID FIRST COUNTER AND A PARTICULAR STATE IN ITS INVERSELY RELATED STAGE IN SAID SECOND COUNTER, AN OUTPUT LINE CONNECTED TO EACH OF SAID GATE CIRCUITS TO RECEIVE THE PULSES PASSING FROM SAID GATE CIRCUITS, AND AN ADDITIONAL PLURALITY OF GATE CIRCUITS, EACH CONNECTED TO THE HIGHEST ORDER STAGES OF SAID SECOND BINARY COUNTER AND OPERATIVE TO DETECT THE ONE OF SAID HIGHEST ORDER STAGES WHICH CONTAINS THE MOST SIGNIFICANT BINARY "ONE" FOR SELECTING THE ASSOCIATED STAGE OF SAID PLURALITY OF STAGES IN SAID FIRST COUNTER AS THE ONE STAGE INTO WHICH THE STREAM OF PULSES REPRESENTING VARIATIONS IN AN INDEPENDENT QUANTITY ARE INTRODUCED.
Claim 2
Dependent Claim 397 words
AN INCREMENTAL INTEGRATOR COMPRISING A FIRST BINARY COUNTER HAVING A PLURALITY OF STAGES, FIRST MEANS FOR INTRODUCING INTO ANY SELECTED ONE OF SAID PLURALITY OF STAGES A STREAM OF PULSES REPRESENTING VARIATIONS IN AN INDEPENDENT QUANTITY TO PRODUCE A PULSE OUTPUT FROM THE LEAST SIGNIFICANT BIT STAGE AT 1/2 OF THE PULSE RATE OF SAID INDEPENDENT QUANTITY, A PULSE OUTPUT FROM THE SECOND LEAST SIGNIFICANT BIT STAGE AT 1/4 OF THE PULSE RATE OF SAID INDEPENDENT QUANTITY ... A PULSE OUTPUT FROM THE MOST SIGNIFICANT BIT STAGE "N" AND 1/2N OF THE PULSE RATE OF SAID INDEPENDENT QUANTITY, A SECOND BINARY COUNTER HAVING AT LEAST THE SAME NUMBER OF STAGES AS SAID FIRST BINARY COUNTER, SECOND MEANS FOR INTRODUCING INTO ANY SELECTED ONE OF SAID PLURALITY OF STAGES OF SAID SECOND COUNTER A STREAM OF PULSES REPRESENTING VARIATIONS IN A DEPENDENT QUANTITY TO PRODUCE A CHANGE IN STATE OF DIFFERENT ONES OF SAID PLURALITY OF STAGES IN SAID SECOND COUNTER, A PLURALITY OF GATE CIRCUITS EACH CONNECTED TO ONE OF THE STAGES OF SAID FIRST COUNTER AND CONNECTED TO ONE OF THE STAGES IN THE SECOND COUNTER IN AN INVERSE RELATIONSHIP WITH THE LEAST SIGNIFICANT BIT STAGE OF SAID FIRST COUNTER AND THE MOST SIGNIFICANT BIT STAGE OF SAID SECOND COUNTER BEING CONNECTED TO A FIRST OF SAID GATE CIRCUITS, THE NEXT LEAST SIGNIFICANT BIT STAGE OF SAID FIRST COUNTER AND THE NEXT MOST SIGNIFICANT BIT STAGE OF THE SECOND COUNTER BEING CONNECTED TO A SECOND OF SAID GATE CIRCUITS ... THE MOST SIGNIFICANT BIT STAGE OF SAID FIRST COUNTER AND SAID LEAST SIGNIFICANT BIT STAGE OF SAID SECOND COUNTER BEING CONNECTED TO AN NTH OF SAID GATE CIRCUITS TO PASS OUTPUT PULSES UPON A PARTICULAR CHANGE OF STATE IN A STAGE OF SAID FIRST COUNTER AND A PARTICULAR STATE IN ITS INVERSELY RELATED STAGE IN SAID SECOND COUNTER, AN OUTPUT LINE CONNECTED TO EACH OF SAID GATE CIRCUITS TO RECEIVE THE PULSES PASSING FROM SAID GATE CIRCUITS, AND AN ADDITIONAL PLURALITY OF GATE CIRCUITS, EACH CONNECTED TO THE HIGHEST ORDER STAGES OF SAID SECOND BINARY COUNTER AND OPERATIVE TO DETECT THE ONE OF SAID HIGHEST ORDER STAGES WHICH CONTAINS THE MOST SIGNIFICANT BINARY "ONE" FOR SELECTING THE ASSOCIATED STAGE OF SAID PLURALITY OF STAGES IN SAID FIRST COUNTER AS THE ONE STAGE INTO WHICH THE STREAM OF PULSES REPRESENTING VARIATIONS IN AN INDEPENDENT QUANTITY ARE INTRODUCED.

References Cited (Backward Citations)

US2841328A Cited
US3050251A Cited
US3029023A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1967-09-08 1968-03-09 1968-09-08 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1971-09-08 1972-03-09 1972-09-08 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1975-09-08 1976-03-09 1976-09-08 $7700.00 Window Closed / Lapsed

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