Character generation system having bold font capability

Claim 2

In a character generation system including character pattern generation means of the Dot matrix type for generating signals representative of a standard font having a plurality of horizontal lines of dots each said dot being selectively controlled by a flip-flop, the improvement comprising; selectively operable means for converting the standard font signal patterns generated by said pattern generation means into a bold font by repeating the last dot of each horizontal line of said standard font comprising N flip-flops, N-1 thereof each having a signal input thereof connected to a separate input terminal of the said converting means, first means for determining which of the N-1 flip-flops change their state when an (N-1)-bit parallel input signal is applied to said input terminals and for determining which one of the flip-flops of changed state is the last one to precede a flip-flop whose state is not changed, and second means for causing said flipflop which is preceded by said last flip-flop of changed state to change its state.

Claim 3

The character generation system as claimed in claim 1 wherein the N flip-flops are connected in cascade to form a shift register, the J and K inputs of each flip-flop except the Nth one being respectively connected to the Q and Q outputs of a preceding flip-flop, wherein the J and K inputs of the Nth flip-flop are respectively connected to earth potential and an electrical supply voltage source, and wherein the output of said converting means is provided by the Q and Q outputs of the first one of said flip-flops.

Claim 4

The character generation system as claimed in claim 2 further including means for driving the shift register.

Claim 5

The character generation system as claimed in claim 1 wherein the Q output of each of the N flip-flops is connected to an output of said converting means.

Claim 6

The character generation system as claimed in claim 1 wherein said first means include a first NAND gate for each one of N-2 of said flip-flops, each one of said first NAND gates having one of its inputs connected to the Q output of the associated flip-flop and its other input(s) connected to the Q output of the following remaining one(s) of the N-1 flip-flops, and a second NAND gate having its output connected to one signal input of the Nth flip-flop and one of its two inputs connected to thE Q output of the (N-1)th flip-flop.

Claim 7

The character generation system as claimed in claim 5 wherein a first invert gate is interposed between each one of the N-1 flip-flops and the associated input terminal.

Claim 8

The character generation system as claimed in claim 6 wherein said second means include a third NAND gate having its inputs connected to the Q outputs of the N-1 flip-flops and its output connected to the input of first pulse generating means and to one of two inputs of each one of N-2 memory elements, a fourth NAND gate for each of the N-2 memory elements, each of said fourth NAND gates having its output connected to the other input of the associated one of the N-2 memory elements and one of its two inputs connected to the output of a separate one of the first NAND gates via a third invert gate, the other input of each of the fourth NAND gates being connected together and to one output of the first pulse generating means, a fifth NAND gate for each one of the N-2 memory elements, each of the fifth NAND gates having one of its two inputs connected to the output of the associated one of the N-2 memory elements, the other of its inputs connected to one output of second pulse generating means and its output connected to one of the two inputs of an OR-gate, the input to the second pulse generating means being connected to another output of the first pulse generating means, and wherein each one of the OR-gates is interposed between the said one signal input of a separate one of the second to the (N-1)th flip-flops of the N-1 flip-flops and the associated one of the first invert gates, the other of the two inputs of each of the OR-gates being connected to the output of the associated first invert gate while the output of each of the OR-gates is connected to the said one signal input of the associated flip-flop.

Claim 9

The character generation system as claimed in claim 7 wherein the first pulse generating means include a first differentiating network, a second invert gate having its input connected to the input of the first generating means and its output connected to the input of the first differentiating network, and a fourth invert gate having its input connected to the output of the first differentiating network and to the said another output of the first generating means and its output connected to the said one output of the generating means.

Claim 10

The character generation system as claimed in claim 7 wherein the second pulse generating means include a second differentiating network having its output connected to one output of the second generating means via a fifth invert gate and to another output of the second generating means, and its input connected to the output of a monostable network, the input of the monostable network being connected to the input of the second generating means.

Claim 11

The character generation system as claimed in claim 8 wherein the other input of the second NAND gate is connected to the output of the second pulse generating means.

Claim 12

The character generation system as claimed in claim 1 further including switching means for selecting a standard font or bold font mode of operation.

Claim 13

The character generation system as claimed in claim 8 further including switching means for selecting a standard font or bold font mode of operation, said switching means being provided by a two-pole, two-way electrical switch, one pole being adapted to switch the output of the second pulse generating means either to the inputs of the second and fifth NAND gates or to earth potential while the other pole is adapted to switch the output of the first pulse generating means either to the inputs of the fourth NAND gates or to earth potential.

Claim 14

The character generation system as claimed in claim 7 further comprising means for driving the shift register, said means for driving the shift register including a memory element having one of its two inputs connected to The output of the third NAND gate and the other of its inputs connected to the said another output of the second pulse generating means, and a sixth NAND gate having its output connected to the drive input of each of the N flip-flops, one of its two inputs connected to the output of the memory element, and the other of its inputs adapted to be connected to an oscillatory input signal.

Claim 15

The character generation system as claimed in claim 13 wherein each of the memory elements include two NAND gates, wherein the output of one of the NAND gates is connected to the output of the respective memory element and to one of the two inputs of the other of the NAND gates, wherein the output of the said other of the NAND gates is connected to one of the two inputs of the said one of the NAND gates, and wherein the two inputs of the memory element are each connected to the other of the inputs of a separate one of the two NAND gates.

Claim 16

The character generation system as claimed in claim 8 wherein each of the differentiating networks include a resistance and a capacitance connected in series between an electrical supply voltage source and the input of the network, the junction of the resistance and the capacitance being connected to the output of the network.

Claim 17

The character generation system as claimed in claim 9 wherein the monostable network includes three NAND gates, wherein the output of the network is connected to the output of one of the three gates, to the two inputs of another of the three gates, and to one of the two inputs of the other of the three gates, wherein the input of the network is connected to one of the two inputs of the said one of the three gates whose other input is connected to the output of the said other of the three gates, and wherein the other input of the said other of the three gates is connected to earth potential via a capacitance and to the output of the said another of the three gates via a resistance.

Claim 18

The character generation system as claimed in claim 2 wherein the N flip-flops each have another signal input thereof connected to an electrical bias network.

Claim 19

The character generation system as claimed in claim 17 wherein the electrical bias network includes a resistance and a capacitance connected in series between an electrical supply voltage source and earth potential, the junction of the resistance and capacitance being connected to the said another signal inputs of the N flip-flops.