Patent US3678475A successfully refreshed from Google Patents.
US3678475A
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US
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Read only memory and method of using same
Assignee: International Business Machines Corp
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Filing: 1971-02-01
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Granted: 1972-07-18
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Expires: 1991-02-01
Abstract
Abstract A method and apparatus for storing in a read only memory a matrix having one or more rows each with a majority of '''' 1'''' bits. There is formed the complement of each of those rows having a majority of '''' 1'''' bits to form a new matrix wherein no row has a majority of '''' 1'''' bits. The new matrix is stored in a read only memory. Upon reading out one or more rows of the matrix the bits of the complemented rows are reinverted.
Inventors
- 👤 Paul V Jordan
- 👤 John A Palmieri
- 👤 William T Wade
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 18:45
CPC Classifications
G; G11; G11C; G11C17/00; G11C17/08
Claims Analysis
Total Claims: 28
Claim 1
Independent Claim
90 words
A method for storing a matrix of a predetermined horizontal dimension and having one or more rows each with a majority of bits of a predetermined value, said method comprising the steps of forming the complement of each of those rows having a majority of said bits of a predetermined value, storing said new matrix in a transistor array of a horizontal dimension less than said matrix horizontal dimension, reading out one or more rows of the stored matrix, and re-inverting the bits of the complemented rows upon readout thereoF.
Claim 2
Independent Claim
90 words
A method for storing a matrix of a predetermined horizontal dimension and having one or more rows each with a majority of bits of a predetermined value, said method comprising the steps of forming the complement of each of those rows having a majority of said bits of a predetermined value, storing said new matrix in a transistor array of a horizontal dimension less than said matrix horizontal dimension, reading out one or more rows of the stored matrix, and re-inverting the bits of the complemented rows upon readout thereoF.
Claim 3
Independent Claim
91 words
A method for storing a matrix of a predetermined horizontal dimension and having one or more rows each with a majority of bits of a predetermined value, said method comprising the steps of forming the complement of each of those rows having a majority of said bits of a predetermined value, storing said new matrix in a transistor array of a horizontal dimension equal to one-half said matrix horizontal dimension, reading out one or more rows of the stored matrix, and re-inverting the bits of the complemented rows upon readout thereof.
Claim 4
Independent Claim
91 words
A method for storing a matrix of a predetermined horizontal dimension and having one or more rows each with a majority of bits of a predetermined value, said method comprising the steps of forming the complement of each of those rows having a majority of said bits of a predetermined value, storing said new matrix in a transistor array of a horizontal dimension equal to one-half said matrix horizontal dimension, reading out one or more rows of the stored matrix, and re-inverting the bits of the complemented rows upon readout thereof.
Claim 5
Independent Claim
102 words
A method for storing a matrix of a predetermined horizontal dimension and having one or more rows each with a majority of bits of a predetermined value, said method comprising the steps of forming the complement of each of those rows having a majority of said bits of a predetermined value to form a new matrix wherein no row has a majority of said bits of a predetermined value, storing said new matrix in a transistor array of a horizontal dimension, reading out one or more rows of the stored matrix, and reinverting the bits of the complemented rows upon readout thereof.
Claim 6
Independent Claim
102 words
A method for storing a matrix of a predetermined horizontal dimension and having one or more rows each with a majority of bits of a predetermined value, said method comprising the steps of forming the complement of each of those rows having a majority of said bits of a predetermined value to form a new matrix wherein no row has a majority of said bits of a predetermined value, storing said new matrix in a transistor array of a horizontal dimension, reading out one or more rows of the stored matrix, and reinverting the bits of the complemented rows upon readout thereof.
Claim 7
Independent Claim
112 words
A method for storing and reading a matrix of predetermined horizontal and vertical dimensions and having one or more rows each with a majority of bits of a predetermined value, said method comprising the steps of forming the complement of each of those rows having a majority of said bits of a predetermined value to form a new matrix wherein no row has a majority of said bits of a predetermined value, storing said new matrix in a transistor array of a horizontal dimension equal to one-half said matrix horizontal dimension, reading out one or more rows of the stored matrix, and re-inverting the bits of the complemented rows upon readout thereof.
Claim 8
Independent Claim
112 words
A method for storing and reading a matrix of predetermined horizontal and vertical dimensions and having one or more rows each with a majority of bits of a predetermined value, said method comprising the steps of forming the complement of each of those rows having a majority of said bits of a predetermined value to form a new matrix wherein no row has a majority of said bits of a predetermined value, storing said new matrix in a transistor array of a horizontal dimension equal to one-half said matrix horizontal dimension, reading out one or more rows of the stored matrix, and re-inverting the bits of the complemented rows upon readout thereof.
Claim 9
Dependent Claim
78 words
A read only memory apparatus for storing a matrix of a predetermined horizontal dimension and having one or more rows each with a majority of bits of a predetermined value, said apparatus comprising means for storing the complements of those rows having a majority of said bits, said storing means including an array of transistors each corresponding to and storing a bit of said predetermined value, said array having a horizontal dimension less than said matrix horizontal dimension.
Claim 10
Dependent Claim
78 words
A read only memory apparatus for storing a matrix of a predetermined horizontal dimension and having one or more rows each with a majority of bits of a predetermined value, said apparatus comprising means for storing the complements of those rows having a majority of said bits, said storing means including an array of transistors each corresponding to and storing a bit of said predetermined value, said array having a horizontal dimension less than said matrix horizontal dimension.
Claim 11
Dependent Claim
79 words
A read only memory apparatus for storing a matrix of a predetermined horizontal dimension and having one or more rows each with a majority of bits of a predetermined value, said apparatus comprising means for storing the complements of those rows having a majority of said bits, said storing means including an array of transistors each corresponding to and storing a bit of said predetermined value, said array having a horizontal dimension equal to one-half said matrix horizontal dimension.
Claim 12
Dependent Claim
79 words
A read only memory apparatus for storing a matrix of a predetermined horizontal dimension and having one or more rows each with a majority of bits of a predetermined value, said apparatus comprising means for storing the complements of those rows having a majority of said bits, said storing means including an array of transistors each corresponding to and storing a bit of said predetermined value, said array having a horizontal dimension equal to one-half said matrix horizontal dimension.
Claim 13
Dependent Claim
82 words
A read only memory for storing a matrix having one or more rows each with a majority of bits of a predetermined value, said memory comprising means for storing the complements of those rows having a majority of said bits and for storing the true values of the other rows, said storing means including an array of transistors each corresponding to and storing a bit of said predetermined value, and means for re-inverting the bits of the complemented rows upon read-out thereof.
Claim 14
Dependent Claim
82 words
A read only memory for storing a matrix having one or more rows each with a majority of bits of a predetermined value, said memory comprising means for storing the complements of those rows having a majority of said bits and for storing the true values of the other rows, said storing means including an array of transistors each corresponding to and storing a bit of said predetermined value, and means for re-inverting the bits of the complemented rows upon read-out thereof.
Claim 15
Dependent Claim
101 words
A read only memory for storing a matrix of a predetermined horizontal dimension and having one or more rows each with a majority of bits of a predetermined value, said memory comprising means for storing the complements of those rows having a majority of said bits and for storing the true values of the other rows, said storing means including an array of transistors having a horizontal dimension equal to one-half said matrix horizontal dimension and each transistor corresponding to and storing a bit of said predetermined value, and means for re-inverting the bits of the complemented rows upon read-out thereof.
Claim 16
Dependent Claim
101 words
A read only memory for storing a matrix of a predetermined horizontal dimension and having one or more rows each with a majority of bits of a predetermined value, said memory comprising means for storing the complements of those rows having a majority of said bits and for storing the true values of the other rows, said storing means including an array of transistors having a horizontal dimension equal to one-half said matrix horizontal dimension and each transistor corresponding to and storing a bit of said predetermined value, and means for re-inverting the bits of the complemented rows upon read-out thereof.
Claim 17
Independent Claim
86 words
A method for storing a matrix of predetermined dimensions and having one or more vectors each with a majority of bits of a predetermined value, said method comprising the steps of forming the complement of each of those vectors having a majority of said bits of a predetermined value, storing said new matrix in a transistor array of a dimension less than said matrix dimension, reading out one or more vectors of the stored matrix, and re-inverting the bits of the complemented vectors upon readout thereof.
Claim 18
Independent Claim
86 words
A method for storing a matrix of predetermined dimensions and having one or more vectors each with a majority of bits of a predetermined value, said method comprising the steps of forming the complement of each of those vectors having a majority of said bits of a predetermined value, storing said new matrix in a transistor array of a dimension less than said matrix dimension, reading out one or more vectors of the stored matrix, and re-inverting the bits of the complemented vectors upon readout thereof.
Claim 19
Independent Claim
90 words
A method for storing a matrix of a predetermined vertical dimension and having one or more columns each with a majority of bits of a predetermined value, said method comprising the steps of forming the complement of each of those columns having a majority of said bits of a predetermined value, storing said new matrix in a transistor array of a vertical dimension less than said matrix vertical dimension, reading out one or more columns of the stored matrix, and re-inverting the bits of the complemented columns upon readout thereof.
Claim 20
Independent Claim
90 words
A method for storing a matrix of a predetermined vertical dimension and having one or more columns each with a majority of bits of a predetermined value, said method comprising the steps of forming the complement of each of those columns having a majority of said bits of a predetermined value, storing said new matrix in a transistor array of a vertical dimension less than said matrix vertical dimension, reading out one or more columns of the stored matrix, and re-inverting the bits of the complemented columns upon readout thereof.
Claim 21
Dependent Claim
79 words
A read only memory apparatus for storing a matrix of a predetermined vector dimension and having one or more vectors each with a majority of bits of a predetermined value, said apparatus comprising means for storing the complements of those vectors having a majority of said bits, said storing means including an array of transistors each corresponding to and storing a bit of said predetermined value, said array having a vector dimension equal to one-half said matrix vector dimension.
Claim 22
Dependent Claim
79 words
A read only memory apparatus for storing a matrix of a predetermined vector dimension and having one or more vectors each with a majority of bits of a predetermined value, said apparatus comprising means for storing the complements of those vectors having a majority of said bits, said storing means including an array of transistors each corresponding to and storing a bit of said predetermined value, said array having a vector dimension equal to one-half said matrix vector dimension.
Claim 23
Dependent Claim
82 words
A read only memory for storing a matrix having one or more vectors each with a majority of bits of a predetermined value, said memory comprising means for storing the complements of those vectors having a majority of said bits and for storing the true values of the other vectors, said storing means including an array of transistors each corresponding to and storing a bit of said predetermined value, and means for re-inverting the bits of the complemented vectors upon read-out thereof.
Claim 24
Dependent Claim
82 words
A read only memory for storing a matrix having one or more vectors each with a majority of bits of a predetermined value, said memory comprising means for storing the complements of those vectors having a majority of said bits and for storing the true values of the other vectors, said storing means including an array of transistors each corresponding to and storing a bit of said predetermined value, and means for re-inverting the bits of the complemented vectors upon read-out thereof.
Claim 25
Dependent Claim
79 words
A read only memory apparatus for storing a matrix of a predetermined vertical dimension and having one or more columns each with a majority of bits of a predetermined value, said apparatus comprising means for storing the complements of those columns having a majority of said bits, said storing means including an array of transistors each corresponding to and storing a bit of said predetermined value, said array having a vertical dimension equal to one-half said matrix vertical dimension.
Claim 26
Dependent Claim
79 words
A read only memory apparatus for storing a matrix of a predetermined vertical dimension and having one or more columns each with a majority of bits of a predetermined value, said apparatus comprising means for storing the complements of those columns having a majority of said bits, said storing means including an array of transistors each corresponding to and storing a bit of said predetermined value, said array having a vertical dimension equal to one-half said matrix vertical dimension.
Claim 27
Dependent Claim
82 words
A read only memory for storing a matrix having one or more columns each with a majority of bits of a predetermined value, said memory comprising means for storing the complements of those columns having a majority of said bits and for storing the true values of the other columns, said storing means including an array of transistors each corresponding to and storing a bit of said predetermined value, and means for re-inverting the bits of the complemented columns upon read-out thereof.
Claim 28
Dependent Claim
82 words
A read only memory for storing a matrix having one or more columns each with a majority of bits of a predetermined value, said memory comprising means for storing the complements of those columns having a majority of said bits and for storing the true values of the other columns, said storing means including an array of transistors each corresponding to and storing a bit of said predetermined value, and means for re-inverting the bits of the complemented columns upon read-out thereof.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-07-18 | 1976-01-17 | 1976-07-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-07-18 | 1980-01-17 | 1980-07-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-07-18 | 1984-01-17 | 1984-07-18 | $7700.00 | Window Closed / Lapsed |