Universal cyclic division circuit

Claim 2

A universal cyclic redundancy check generator comprising: a first register means for storing the cyclic division polynomial; a second register means for storing a previously calculated cyclic redundancy check remainder; a third register means for storing the new data remainder for which a new cyclic redundancy check term is to be calculated; and a rectangular array calculating means for simultaneously combining the data from said first register means, said second register means and said third register means to simultaneously produce the terms of a new cyclic redundancy check remainder from the polynomial, the old cyclic redundancy check remainder, and the new data character.

Claim 3

The universal cyclic redundancy check generator as in claim 1 additionally comprising: a storage means responsive to said array calculating means for storing said new cyclic redundancy check remainder for use in subsequent operations of said cyclic redundancy check generator as said previously calculated cyclic redundancy check remainder for each of a plurality of communication channels.

Claim 4

The universal cyclic redundancy check generator of claim 2 additionally comprising: an address register for storing addresses of external communication devices for which a cyclic redundancy check remainder is to be generated; a storage addressing means responsive to said address register for addressing said storage means to access information therein, said information comprising a cyclic division polynomial and a previously calculated cyclic redundancy check remainder; and means for transmitting said previously calculated cyclic redundancy check remainder from said storage means to said old cyclic redundancy check register and for transmitting said cyclic division polynomial from said storage means to said polynomial register.

Claim 5

A universal cyclic redundancy check generator for generating cyclic redundancy check remainders from transmitted data characters comprising: an array of cell elements, each cell element having a first input, a second input, a third input and an output, said cell elements being arranged in m columns and n rows of elements, each element being identified as cell element Ci,j where i represents the number of the row and j represents the number of the column in which a cell element is located; a polynomial register containing m binary bit positions, each of said binary bit positions of said polynomial register being wired to the second input of all cell elements in a single unique column in said array of cell element; an old cyclic redundancy check register containing m binary bit positions; a new character register containing no more than n binary bit positions; a new cyclic redundancy check register containing m binary bit positions; interconnections connecting the output of each cell element Ci, j, where i has a value between 0 and n-1 and j has a value between 0 and m-1 to the third input to cell element Ci 1, j 1; interconnections connecting the output of each cell element Ci,m where i has a value between 0 and n-1 to said first input of the cell elements Ci 1, j where j has a value range from 0 to m; means for connecting the third input of each cell element C0,j where j takes on values from 0 to n to a source for placing a binary 0 value upon each of said third inputs of said cell elements C0,j; a half sum means responsive to said new character register and said old CRC register for generating a half sum; an interconnection to place the lowest order bit signal of half sum means upon the intermediate feedback connection which connects all of the first inputs of the cell elements in row 0 of the array of cell elements; interconnections for connecting bits 0 through m-1 of said half sum to the third inputs of the cell elements C0,1 through cell elements C0,m; and gating means for gating the output of each said cell elements Ci,j to said new cyclic redundancy check register where i equals the number of bits in the data character in said new character register and j takes on all values from 0 to m.

Claim 6

A universal cyclic redundancy check generator for generating cyclic redundancy check remainders from transmitted data characters comprising: an array of cell elements, each cell element having a first input, a second input, a third input and an output, said cell elements being arranged in m columns and n rows of elements, each element being identified as cell element Ci,j where i represents the number of the row and j represents the number of the column in which a cell element is located; a polynomial register containing m binary bit positions, each of said binary bit positions of said polynomial register being wired to the second input of all cell elements in a single unique column in said array of cell element; an old cyclic redundancy check register containing m binary bit positions; a new character register containing no more than n binary bit positions; a new cyclic redundancy check register containing m binary bit positions; interconnections connecting the output of each cell element Ci, j, where i has a value between 0 and n-1 and j has a value between 0 and m-1 to the third input to cell element Ci 1, j 1; interconnections connecting the output of each cell element Ci,m where i has a value between 0 and n-1 to said first input of the cell elements Ci 1, j where j has a value range from 0 to m; means for connecting the third input of each cell element C0,j where j takes on values from 0 to n to a source for placing a binary 0 value upon each of said third inputs of said cell elements C0,j; a half sum means responsive to said new character register and said old CRC register for generating a half sum; an interconnection to place the lowest order bit signal of half sum means upon the intermediate feedback connection which connects all of the first inputs of the cell elements in row 0 of the array of cell elements; interconnections for connecting bits 0 through m-1 of said half sum to the third inputs of the cell elements C0,1 through cell elements C0,m; and gating means for gating the output of each said cell elements Ci,j to said new cyclic redundancy check register where i equals the number of bits in the data character in said new character register and j takes on all values from 0 to m.

Claim 7

A universal cyclic redundancy check generator as in claim 4 wherein said cell elements comprise: an AND circuit having two inputs and one output; an EXCLUSIVE OR circuit having two inputs and one output; said first and second inputs to said AND circuits comprising said first and second inputs to said cell element; an interconnecting circuit for connecting said output of said AND circuit to one input of said EXCLUSIVE OR circuit; the remaining input to said EXCLUSIVE OR circuit comprises said third input to said cell element; and said output of said EXCLUSIVE OR element comprises said output of said cell element.

Claim 8

A universal cyclic redundancy check generator for generating cyclic redundancy check remainders from transmitted data characters comprising: an array of cell elements, each cell element having a first input, a second input, a third input and an output, said cell elements being arranged in m columns and n rows of elements, each element being identified as cell element Ci,j where i represents the number of the row and j represents the number of the column in which a cell element is located; a polynomial register containing m binary bit position, each of said binary bit positions of said polynomial register being wired to the second input of all cell elements in a single unique column in said array of cell element; an old cyclic redundancy check register containing m binary bit positions; a new character register containing no more than n binary bit positions; a new cyclic redundancy check register containing m binary bit positions; interconnections connecting the output of each cell element Ci, j, where i has a value between 0 and n-1 and j has a value between 0 and m-1 to the third input to cell element Ci 1, j 1; interconnections connecting the output of each cell element Ci,m, where i has a value between 0 and n-1 to said first input of the elements Ci 1, j where j has a value range from 0 to m; means for connecting the third input of each cell element C0,j where j takes on values from 0 to n to a source for placing a binary 0 value upon each of said third inputs of said cell elements C0,j; n EXCLUSIVE OR circuits, each circuit having two inputs and an output, one input of each of said EXCLUSIVE OR circuits being connected to a single unique binary bit position of said new character register and a second input of each of said EXCLUSIVE OR circuits being connected to a corresponding unique low order bit position of said old cyclic redundancy check register, the outputs of the n-1 highest order EXCLUSIVE OR circuits being connected to a single unique third input of said cell elemEnts Ci,j where i equals 0 and j takes on values from m-n to m-1, the lowest order output of said EXCLUSIVE OR circuits is wired to the first input of each of said cell elements Ci,j where i equals 0 and j takes on all values from 0 to m; interconnecting circuits for connecting the highest order bit positions of said old cyclic redundancy check register to corresponding single third inputs of said cell elements Ci,j where i equals 0 and j takes on values from 0 to m-(n-1); and gating means for gating the output of each of said cell elements Ci,j to said new cyclic redundancy check register where i equals the number of bits in the data character in said new character register and j takes on all values from 0 to m.

Claim 9

A universal cyclic redundancy check generator for generating cyclic redundancy check remainders from transmitted data characters comprising: an array of cell elements, each cell element having a first input, a second input, a third input and an output, said cell elements being arranged in m columns and n rows of elements, each element being identified as cell element Ci,j where i represents the number of the row and j represents the number of the column in which a cell element is located; a polynomial register containing m binary bit position, each of said binary bit positions of said polynomial register being wired to the second input of all cell elements in a single unique column in said array of cell element; an old cyclic redundancy check register containing m binary bit positions; a new character register containing no more than n binary bit positions; a new cyclic redundancy check register containing m binary bit positions; interconnections connecting the output of each cell element Ci, j, where i has a value between 0 and n-1 and j has a value between 0 and m-1 to the third input to cell element Ci 1, j 1; interconnections connecting the output of each cell element Ci,m, where i has a value between 0 and n-1 to said first input of the elements Ci 1, j where j has a value range from 0 to m; means for connecting the third input of each cell element C0,j where j takes on values from 0 to n to a source for placing a binary 0 value upon each of said third inputs of said cell elements C0,j; n EXCLUSIVE OR circuits, each circuit having two inputs and an output, one input of each of said EXCLUSIVE OR circuits being connected to a single unique binary bit position of said new character register and a second input of each of said EXCLUSIVE OR circuits being connected to a corresponding unique low order bit position of said old cyclic redundancy check register, the outputs of the n-1 highest order EXCLUSIVE OR circuits being connected to a single unique third input of said cell elemEnts Ci,j where i equals 0 and j takes on values from m-n to m-1, the lowest order output of said EXCLUSIVE OR circuits is wired to the first input of each of said cell elements Ci,j where i equals 0 and j takes on all values from 0 to m; interconnecting circuits for connecting the highest order bit positions of said old cyclic redundancy check register to corresponding single third inputs of said cell elements Ci,j where i equals 0 and j takes on values from 0 to m-(n-1); and gating means for gating the output of each of said cell elements Ci,j to said new cyclic redundancy check register where i equals the number of bits in the data character in said new character register and j takes on all values from 0 to m.

Claim 10

A universal cyclic redundancy check generator as in claim 6 wherein said cell elements comprise: an AND circuit having two inputs and one output; an EXCLUSIVE OR circuit having two inputs and one output; said first and second inputs to said AND circuits comprising said first and second inputs to said cell element; an interconnecting circuit for connecting said output of said AND circuit to one input of said EXCLUSIVE OR circuit; the remaining input to said EXCLUSIVE OR circuit comprises said third input to said cell element; and said output of said EXCLUSIVE OR element comprises said output of said cell element.