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US3676600A
Expired / Lapsed
US
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Nonlinear encoder
Assignee: NEC Corp
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Filing: 1970-06-22
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Granted: 1972-07-11
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Expires: 1990-06-22
Abstract
Abstract A multi-bit nonlinear apparatus for encoding an amplitude modulation pulse analog signal of positive and negative polarities into a series of bits in a pulse code modulation system, including two non-linear direct current amplifier stages for translating the input analog signal into first and second serial bits, and a mutli-stage feedback logic encoder for providing subsequent serial bits.
Inventors
- 👤 Harue Kaneko Kaeru Yane
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 14:16
CPC Classifications
H; H04; H04B; H04B14/00; H04B14/02; H04B14/04; H04B14/046; H04B14/048; H03; H03M; H03M1/00; H03M1/12; H03M1/124
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
466 words
A multi-bit nonlinear apparatus for encoding a pulse analog signal into a preselected number of serial bits, comprising: a source of a pulse amplitude modulation analog signal varying in negative and positive polarities; means for translating said analog signal into a first bit and an output signal portion alternately provided with one of a zero magnitude and a predetermined magnitude of negative polarity; first AND gate means for reading out said first bit from said translating means; an OR gate for transmitting said first bit from said first AND gate means; an output terminal for receiving said first bit from said OR gate to constitute a first of said encoded serial bits; means including a direct current amplifier having an input activated by said translating means output signal portion and an output connected through two different feedback paths to said last-mentioned input for converting said translating means output signal portion into a second bit; second AND gate means reading out said second bit from said converting means for transmission through said OR gate to said output terminal as a second of said encoded serial bits; a supply of direct current of predetermined magnitude and positive polarity applied as a biasing current to an input of said converting means to constitute a positive decision level for said second bit; a generator activated by a ''''0'''' second bit received from an output of said converting means for providing an output current having a negative polarity and a magnitude equal to said supply current predetermined magnitude to constitute a negative decision level for said second bit; and sequential feedback means for supplying subsequent serial bits to said encoded serial bits, including: decoder means activated by a preselected timing signal to provide an output current of decision level for a third bit; an adder circuit having an input connected to said supply, said amplifier two feedback paths, said generator output and an output of said decoder means for adding output currents of said amplifier two feedback paths and said decoder means to provide an output having one of positive and negative polarities at a given time; comparator means responsive to said adder circuit output to provide a third bit; third AND gate means for reading out said third bit from said comparator means for transmission through said OR gate to said output terminal as a third in said encoded serial bits; logic means responsive to said read-out third bit for further activating said decoder means to provide an output current of decision level for a fourth bit; said adder circuit, said comparator circuit and said third AND gate means responsive in turn to said fourth bit decision level current to transmit a fourth bit through said OR gate to said output terminal as a fourth in said encoded serial bits.
Claim 2
Dependent Claim
466 words
A multi-bit nonlinear apparatus for encoding a pulse analog signal into a preselected number of serial bits, comprising: a source of a pulse amplitude modulation analog signal varying in negative and positive polarities; means for translating said analog signal into a first bit and an output signal portion alternately provided with one of a zero magnitude and a predetermined magnitude of negative polarity; first AND gate means for reading out said first bit from said translating means; an OR gate for transmitting said first bit from said first AND gate means; an output terminal for receiving said first bit from said OR gate to constitute a first of said encoded serial bits; means including a direct current amplifier having an input activated by said translating means output signal portion and an output connected through two different feedback paths to said last-mentioned input for converting said translating means output signal portion into a second bit; second AND gate means reading out said second bit from said converting means for transmission through said OR gate to said output terminal as a second of said encoded serial bits; a supply of direct current of predetermined magnitude and positive polarity applied as a biasing current to an input of said converting means to constitute a positive decision level for said second bit; a generator activated by a ''''0'''' second bit received from an output of said converting means for providing an output current having a negative polarity and a magnitude equal to said supply current predetermined magnitude to constitute a negative decision level for said second bit; and sequential feedback means for supplying subsequent serial bits to said encoded serial bits, including: decoder means activated by a preselected timing signal to provide an output current of decision level for a third bit; an adder circuit having an input connected to said supply, said amplifier two feedback paths, said generator output and an output of said decoder means for adding output currents of said amplifier two feedback paths and said decoder means to provide an output having one of positive and negative polarities at a given time; comparator means responsive to said adder circuit output to provide a third bit; third AND gate means for reading out said third bit from said comparator means for transmission through said OR gate to said output terminal as a third in said encoded serial bits; logic means responsive to said read-out third bit for further activating said decoder means to provide an output current of decision level for a fourth bit; said adder circuit, said comparator circuit and said third AND gate means responsive in turn to said fourth bit decision level current to transmit a fourth bit through said OR gate to said output terminal as a fourth in said encoded serial bits.
Claim 3
Dependent Claim
75 words
The apparatus according to claim 1 in which said decoder means comprises a memory circuit including normally reset first and second flip-flops of which said first flip-flop is set in response to a preselecteD timing signal while said second flip-flop remains reset for providing ''''1'''' and ''''0'''' at said first and second flip-flop set outputs, respectively, and thereby ''''1 0'''' at an output of said memory circuit to represent said third bit decision level current.
Claim 4
Dependent Claim
58 words
The apparatus according to claim 2 in which said decoder means includes an AND gate matrix embodying three AND gates, each having one output and two inputs so connected to set and inversion outputs of said first and second flip-flops as to activate said matrix to provide a ''''010'''' output to represent said third bit decision level current.
Claim 5
Dependent Claim
68 words
The apparatus according to claim 3 in which said decoder means includes a drive circuit embodying second, third and fourth current generators, each having an input connected to said output of one of said matrix AND gates in said matrix and also having an output; said drive circuit generators selectively actuated in response to said AND gate matrix output ''''010'''' to represent said third bit decision level current.
Claim 6
Dependent Claim
58 words
The apparatus according to claim 4 in which said decoder means includes a resistor ladder network embodying three parallel resistors and three series resistors so interconnected therebetween and to said outputs of said respective drive generators as to energize said resistors in response to said last-mentioned selectively actuated drive generators to provide said third bit decision level current.
Claim 7
Dependent Claim
59 words
The apparatus according to claim 5 in which said decoder means second flip-flop is set in response to a preselected second timing signal while said first-flop is still set for providing ''''1'''' and ''''1'''' at said first and second flip-flop set outputs, respectively, thereby providing ''''11'''' at said memory circuit output to represent said fourth bit decision level current.
Claim 8
Dependent Claim
40 words
The apparatus according to claim 6 in which said AND gate matrix further responsive to said memory circuit output ''''11'''' changes said last-mentioned matrix from said ''''010'''' output to a ''''100'''' output to represent said fourth bit decision level current.
Claim 9
Dependent Claim
36 words
The apparatus according to claim 7 in which said drive circuit second, third and fourth generators are selectively activated in response to said AND gate matrix output ''''100'''' to represent said fourth bit decision level current.
Claim 10
Dependent Claim
33 words
The apparatus according to claim 8 in which said resistor ladder network resistors are energized in response to said last-mentioned drive circuit selectively activated generators to provide said fourth bit decision level current.
Claim 11
Dependent Claim
346 words
The apparatus according to claim 1 in which said decoder means comprises: a memory circuit including: first and second flip-flops which are normally reset; said first flip-flop is thereafter set in response to a first preselected timing signal which said second flip-flop remains reset for providing ''''1'''' and ''''0'''' at said first and second flip-flop set outputs, respectively, and thereby ''''10'''' at an output of memory circuit to represent said third bit decision level current; an AND gate matrix embodying three AND gates, each having one output and two inputs so interconnected to set and inversion outputs of said first and second flip-flops as to actuate said matrix to provide a ''''010'''' output to represent said third bit decision level current; a drive circuit embodying second, third and fourth current generators, each having an output and an input connected to said output of one of said matrix AND gates; said drive generators selectively activated in response to said AND gate matrix output ''''010'''' to represent said third bit decision level current; a resistor ladder network embodying three parallel resistors and three series resistors so interconnected therebetween and to said respective drive generator outputs as to energize said resistors in response to said last-mentioned selectively activated drive generators to provide said third bit decision level current; said second flip-flop set in response to a preselected second timing signal while said first flip-flop remains set for providing ''''1'''' and ''''1'''' at said first and second flip-flop set outputs, respectively, thereby providing ''''11'''' at said memory circuit output to represent said fourth bit decision level current; said AND gate matrix further responsive to said memory circuit output ''''11'''' to change said last-mentioned matrix from said ''''010'''' output to a ''''100'''' output to represent said fourth bit decision level current; said drive circuit current generators further selectively activated in response to said AND gate matrix output ''''100'''' to represent said fourth bit decision level current; and said resistor ladder network resistors are further energized by said last-mentioned drive circuit selectively activated generators to provide said fourth bit decision level current.
Claim 12
Dependent Claim
373 words
A multi-bit nonlinear apparatus for encoding a pulse analog signal into a preselected number of serial bits, comprising: a source of a pulse amplitude modulation analog signal varying in negative and positive polarities; means for translating said analog signal into a first bit and an output signal portion alternately provided with one of a zero magnitude and a predetermined magnitude of one of said negative and positive polarities; means including a direct current amplifier having an input activated by said translating means output signal portion and an output connected through two different feedback paths to said last-mentioned input for converting said translating means output signal portion into a second bit; a supply of direct current of predetermined magnitude and the other of said polarities applied as a biasing current to an input of said converting means to constitute a decision level of said other polarity for said second bit; a generator activated by said second bit received from an output of said converting means for providing an out-put current having said one polarity and a magnitude equal to said supply current of predetermined magnitude to constitute a decision level of said one polarity for said second bit; sequential feedback means for determining subsequent serial bits including (a) decoder means activated by a preselected timing signal to provide an output current of decision level for a third bit, (b) an adder circuit having an input connected to said supply, said amplifier two feedback paths, said generator output and output of said decoder means for adding output currents of said amplifier two feedback paths and said decoder means to provide an output having one of the positive and negative polarities at a given time, (c) comparator means responsive to said adder circuit output to provide a third bit, and (d) first logic means responsive to said third bit for further activating said decoder means to provide an output current of decision level for a fourth bit, said adder circuit and said comparator circuit responsive in turn to said fourth bit decision level current to determine a fourth bit; and second logic means for combining said first, second, third and fourth bits to obtain said preselected number of serial bits as the output of said apparatus.
Claim 13
Dependent Claim
373 words
A multi-bit nonlinear apparatus for encoding a pulse analog signal into a preselected number of serial bits, comprising: a source of a pulse amplitude modulation analog signal varying in negative and positive polarities; means for translating said analog signal into a first bit and an output signal portion alternately provided with one of a zero magnitude and a predetermined magnitude of one of said negative and positive polarities; means including a direct current amplifier having an input activated by said translating means output signal portion and an output connected through two different feedback paths to said last-mentioned input for converting said translating means output signal portion into a second bit; a supply of direct current of predetermined magnitude and the other of said polarities applied as a biasing current to an input of said converting means to constitute a decision level of said other polarity for said second bit; a generator activated by said second bit received from an output of said converting means for providing an out-put current having said one polarity and a magnitude equal to said supply current of predetermined magnitude to constitute a decision level of said one polarity for said second bit; sequential feedback means for determining subsequent serial bits including (a) decoder means activated by a preselected timing signal to provide an output current of decision level for a third bit, (b) an adder circuit having an input connected to said supply, said amplifier two feedback paths, said generator output and output of said decoder means for adding output currents of said amplifier two feedback paths and said decoder means to provide an output having one of the positive and negative polarities at a given time, (c) comparator means responsive to said adder circuit output to provide a third bit, and (d) first logic means responsive to said third bit for further activating said decoder means to provide an output current of decision level for a fourth bit, said adder circuit and said comparator circuit responsive in turn to said fourth bit decision level current to determine a fourth bit; and second logic means for combining said first, second, third and fourth bits to obtain said preselected number of serial bits as the output of said apparatus.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-07-11 | 1976-01-10 | 1976-07-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-07-11 | 1980-01-10 | 1980-07-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-07-11 | 1984-01-10 | 1984-07-11 | $7700.00 | Window Closed / Lapsed |