Unlimited roll keyboard circuit

Claim 2

An unlimited roll keyboard circuit for controlling the flow of a key code of any newly depressed key to a key code data collector means during the continued depression of any other key, comprising: a. keyboard switch means having a plurality of key means therein for sending out a binary bit from each depressed key means during each timing cycle; b. an array of bistable means, the keyboard switch means being connected to a first section of the array of bistable means for allowing the inputting of a binary bit from each depressed key means into the first section of the array; c. timing means for transferring the binary bits from the first section of the array of bistable means serially into a second section of the array of bistable means during a timing cycle; d. compare means for comparing the binary bitsserially coming out of the first section of the array of bistable means with the binary bits serially coming out of the second section of the array of bistable means, during any timing cycle.

Claim 3

An unlimited roll keyboard circuit having full-roll capability for controlling the flow of a key code of any newly depressed key to a key code data collector means during the continued depression of any other key, comprising: a. keyboard switch means having a plurality of key means therein for sending out a binary bit from each depressed key means during each timing cycle; b. an array of shift register cells, the keyboard switch means being connected to a first section of the array of shift register cells for allowing the inputting of a binary bit from each depressed key means into a shift register cell of the first section of the array; c. timing means for transferring the binary bits from the first section of the array of shift register cells serially into a second section of the array of shift register cells during a timing cycle; d. compare means for comparing the binary bits serially coming out of the first section of the array of shift register cells with the binary bits serially coming out of the second section of the array oF, shift register cells during any timing cycle.

Claim 4

An unlimited roll keyboard circuit having full-roll capability for controlling the flow of a key code of any newly depressed key to a key code data collector means during the continued depression of any other key, comprising: a. keyboard switch means having a plurality of key means therein for sending out a binary bit from each depressed key means during each timing cycle; b. an array of shift register cells, the keyboard switch means being connected to a first section of the array of shift register cells for allowing the inputting of a binary bit from each depressed key means into a shift register cell of the first section of the array; c. timing means for transferring the binary bits from the first section of the array of shift register cells serially into a second section of the array of shift register cells during a timing cycle; d. compare means for comparing the binary bits serially coming out of the first section of the array of shift register cells with the binary bits serially coming out of the second section of the array oF, shift register cells during any timing cycle.

Claim 5

An unlimited roll keyboard circuit for controlling the flow of a binary key code of any newly depressed key to a key code data collector means during the continued depression of any other key, comprising: a. keyboard switch means having a plurality of key means therein for sending out a one bit from each depressed key means during each timing cycle; b. an array of shift register cells, the keyboard switch means being connected to a first section of the array of shift register cells for allowing the inputting of a one bit from each depressed key means into a shift register cell of the first section of the array; c. timing means for transferring the one bits from the first section of the array of shift register cells serially into a second section of the array of shift register cells during each timing cycle; d. a logic AND gate for comparing the binary bits serially coming of of the first section of the array of shift register cells with the binary bits coming out of the second section of the array of shift register cells, during any timing cycle, the logic AND gate sending out a one bit when a one bit comes out of the first section of the array and a zero bit, which is then inverted by an inverter, comes out of the second section of the array during the serial exiting of binary bits from the first and second section of the array of shift register cells during each timing cycle, the one bit out of the logic AND gate allowing a key code to flow to the key code data collector means.

Claim 6

An unlimited roll keyboard circuit for controlling the flow of a binary key code of any newly depressed key to a key code data collector means during the continued depression of any other key, comprising: a. keyboard switch means having a plurality of key means therein for sending out a one bit from each depressed key means during each timing cycle; b. an array of shift register cells, the keyboard switch means being connected to a first section of the array of shift register cells for allowing the inputting of a one bit from each depressed key means into a shift register cell of the first section of the array; c. timing means for transferring the one bits from the first section of the array of shift register cells serially into a second section of the array of shift register cells during each timing cycle; d. a logic AND gate for comparing the binary bits serially coming of of the first section of the array of shift register cells with the binary bits coming out of the second section of the array of shift register cells, during any timing cycle, the logic AND gate sending out a one bit when a one bit comes out of the first section of the array and a zero bit, which is then inverted by an inverter, comes out of the second section of the array during the serial exiting of binary bits from the first and second section of the array of shift register cells during each timing cycle, the one bit out of the logic AND gate allowing a key code to flow to the key code data collector means.

Claim 7

An unlimited roll keyboard encoder circuit for controlling the flow of information by means of any newly depressed key within the keyboard encoder circuit before any formerly depressed keys of the keyboard have been returned to their undepressed positions, comprising: a. a strobe pulse circuit means for generating an intermediate strobe pulse at the beginning of each timing cycle; b. a clock pulse means for generating clock pulses at and intermediately of said strobe pulses during each timing cycle; c. a keyboard having a plurality of switches therein, each switch being connected to a different key within the keyboard for sending out a one bit from each depressed key during each timing cycle; d. a first shift register cell array, each of whose shift register cells is connected to a different switch of the keyboard, any depressed key in the keyboard causing the loading of a one bit in its associated shift register cell, at the strobe pulse during each timing cycle; e. a second shift register cell array having the same number of shift register cells as the first shift register array, being connected to the output of the first shift register array, the second shift register cell array serially receiving information out of the first shift register cell array at each timing cycle; f. a compare circuit means for comparing, during each timing cycle, the binary bit out of the last cell of the first shift register cell array with the binary bit out of the last cell of the second shift register cell array allowing the compare circuit to send out a one bit when a one bit comes out of the first shift register cell array and a zero binary bit, which is then inverted by an inverter, comes out of the second shift register cell array during each timing cycle; g. A counter means for generating a different key code at each clock pulse during each timing cycle and for generating the strobe pulses; h. a key code data-collector means which can be encoded by the counter means at any clock pulse during each timing cycle; and i. a code transfer means which is driven by said compare circuit means connected between the counter means and the key code data collector means for transferring a key code at any clock pulse to the key data collector means only when said one bit comes out of the compare circuit means.

Claim 8

An unlimited roll keyboard encoder circuit for controlling the flow of information by means of any newly depressed key within the keyboard encoder circuit before any formerly depressed keys of the keyboard have been returned to their undepressed positions, comprising: a. a strobe pulse circuit means for generating an intermediate strobe pulse at the beginning of each timing cycle; b. a clock pulse means for generating clock pulses at and intermediately of said strobe pulses during each timing cycle; c. a keyboard having a plurality of switches therein, each switch being connected to a different key within the keyboard for sending out a one bit from each depressed key during each timing cycle; d. a first shift register cell array, each of whose shift register cells is connected to a different switch of the keyboard, any depressed key in the keyboard causing the loading of a one bit in its associated shift register cell, at the strobe pulse during each timing cycle; e. a second shift register cell array having the same number of shift register cells as the first shift register array, being connected to the output of the first shift register array, the second shift register cell array serially receiving information out of the first shift register cell array at each timing cycle; f. a compare circuit means for comparing, during each timing cycle, the binary bit out of the last cell of the first shift register cell array with the binary bit out of the last cell of the second shift register cell array allowing the compare circuit to send out a one bit when a one bit comes out of the first shift register cell array and a zero binary bit, which is then inverted by an inverter, comes out of the second shift register cell array during each timing cycle; g. A counter means for generating a different key code at each clock pulse during each timing cycle and for generating the strobe pulses; h. a key code data-collector means which can be encoded by the counter means at any clock pulse during each timing cycle; and i. a code transfer means which is driven by said compare circuit means connected between the counter means and the key code data collector means for transferring a key code at any clock pulse to the key data collector means only when said one bit comes out of the compare circuit means.

Claim 9

An unlimited roll keyboard encoder circuit for controlling the flow of iNformation by means of any newly depressed key within the keyboard encoder circuit before any formerly depressed keys of the keyboard have been returned to their undepressed positions, comprising: a. a strobe pulse circuit means for a generating intermediate strobe pulse at the beginning of each timing cycle; b. a clock pulse circuit for generating clock pulses intermediately of said strobe pulses during each timing cycle; c. a keyboard having a plurality of switches therein, each switch being connected to a different key within the keyboard for sending out a one bit from each depressed key at each strobe pulse during each timing cycle; d. a first shift register cell array, each of whose shift register cells is connected to a different switch of the keyboard, any depressed key in the keyboard causing the loading of a one bit in its associated shift register cell at the strobe pulse during each timing cycle; e. a second shift register cell array having the same number of shift register cells as the first shift register cell array, being connected to the output of the first shift register cell array, the second shift register cell array serially receiving information out of the first shift register cell array at each timing cycle; f. a logic AND gate for comparing, during each timing cycle, the binary bit out of the last cell of the first shift register cell array with the binary bit out of the last cell of the second shift register cell array allowing the logic AND gate to send out a one bit when a one bit comes out of the first shift register cell array and a zero bit, which is then inverted by an inverter, comes out of the second shift register cell array during each timing cycle; g. a polynomial counter for generating a different key code at each clock pulse during each timing cycle and for generating the strobe pulses; h. a key code data collector means which can be encoded by the polynomial counter at any clock pulse during each timing cycle; and i. a code transfer circuit connected between the polynomial counter and the key code data collector means for transferring a key code at any clock pulse to the key code data collector means when a one bit comes out of the logic AND gate.

Claim 10

An unlimited roll keyboard encoder circuit for controlling the flow of iNformation by means of any newly depressed key within the keyboard encoder circuit before any formerly depressed keys of the keyboard have been returned to their undepressed positions, comprising: a. a strobe pulse circuit means for a generating intermediate strobe pulse at the beginning of each timing cycle; b. a clock pulse circuit for generating clock pulses intermediately of said strobe pulses during each timing cycle; c. a keyboard having a plurality of switches therein, each switch being connected to a different key within the keyboard for sending out a one bit from each depressed key at each strobe pulse during each timing cycle; d. a first shift register cell array, each of whose shift register cells is connected to a different switch of the keyboard, any depressed key in the keyboard causing the loading of a one bit in its associated shift register cell at the strobe pulse during each timing cycle; e. a second shift register cell array having the same number of shift register cells as the first shift register cell array, being connected to the output of the first shift register cell array, the second shift register cell array serially receiving information out of the first shift register cell array at each timing cycle; f. a logic AND gate for comparing, during each timing cycle, the binary bit out of the last cell of the first shift register cell array with the binary bit out of the last cell of the second shift register cell array allowing the logic AND gate to send out a one bit when a one bit comes out of the first shift register cell array and a zero bit, which is then inverted by an inverter, comes out of the second shift register cell array during each timing cycle; g. a polynomial counter for generating a different key code at each clock pulse during each timing cycle and for generating the strobe pulses; h. a key code data collector means which can be encoded by the polynomial counter at any clock pulse during each timing cycle; and i. a code transfer circuit connected between the polynomial counter and the key code data collector means for transferring a key code at any clock pulse to the key code data collector means when a one bit comes out of the logic AND gate.

Claim 11

A keyboard encoder circuit for controlling the flow of information by means of any newly depressed key within the keyboard encoder circuit before any formerly depressed keys of the keyboard have been returned to their undepressed positions, comprising: a. a strobe pulse circuit for generating an intermediate strobe pulse at the beginning of each timing cycle; b. a clock pulse circuit for generating clock pulses intermediately of said strobe pulses during each timing cycle; c. a reset pulse circuit for generating a reset pulse at the first clock time after every strobe pulse; d. a keyboard having a plurality of reed switches therein, each reed switch being connected to a different key within the keyboard, for sending out a one bit from each depressed key at each strobe pulse, by means of capacitors which are charged by the reed switches and discharged by the reset pulse; e. a first shift register cell array, each of whose shift register cells is connected to a different switch of the keyboard, any depressed key in the keyboard causing the loading of a one bit in its associated shift register cell at the strobe pulse during each timing cycle; f. a second shift register cell array having the same number of shift register cells as the first shift register array being connected to the output of the first shift register cell array, the second shift register cell array serially receiving information out of the first shift register cell array at each timing cycle; g. a logic AND gate for comparing, during each timing cycle, the binary bit out of the last cell of the first shift register cell array with the binary bit out of the last cell of the second shift register cell array allowing the logic AND gate to sEnd out a one bit when a one bit comes out of the first shift register cell array and a zero bit, which is then inverted, comes out of the second shift register cell array during each timing cycle; h. a polynomial counter for generating a different key code at each clock pulse during each timing cycle and for generating the strobe pulses; i. a key code data collector device which can be encoded by the polynomial counter at any clock pulse during each timing cycle; and j. a code transfer circuit connected between the polynomial counter and the key code data collector device for transferring a key code at any clock pulse to the key code data collector device when a one bit comes out of the logic AND gate.

Claim 12

A keyboard encoder circuit for controlling the flow of information by means of any newly depressed key within the keyboard encoder circuit before any formerly depressed keys of the keyboard have been returned to their undepressed positions, comprising: a. a strobe pulse circuit for generating an intermediate strobe pulse at the beginning of each timing cycle; b. a clock pulse circuit for generating clock pulses intermediately of said strobe pulses during each timing cycle; c. a reset pulse circuit for generating a reset pulse at the first clock time after every strobe pulse; d. a keyboard having a plurality of reed switches therein, each reed switch being connected to a different key within the keyboard, for sending out a one bit from each depressed key at each strobe pulse, by means of capacitors which are charged by the reed switches and discharged by the reset pulse; e. a first shift register cell array, each of whose shift register cells is connected to a different switch of the keyboard, any depressed key in the keyboard causing the loading of a one bit in its associated shift register cell at the strobe pulse during each timing cycle; f. a second shift register cell array having the same number of shift register cells as the first shift register array being connected to the output of the first shift register cell array, the second shift register cell array serially receiving information out of the first shift register cell array at each timing cycle; g. a logic AND gate for comparing, during each timing cycle, the binary bit out of the last cell of the first shift register cell array with the binary bit out of the last cell of the second shift register cell array allowing the logic AND gate to sEnd out a one bit when a one bit comes out of the first shift register cell array and a zero bit, which is then inverted, comes out of the second shift register cell array during each timing cycle; h. a polynomial counter for generating a different key code at each clock pulse during each timing cycle and for generating the strobe pulses; i. a key code data collector device which can be encoded by the polynomial counter at any clock pulse during each timing cycle; and j. a code transfer circuit connected between the polynomial counter and the key code data collector device for transferring a key code at any clock pulse to the key code data collector device when a one bit comes out of the logic AND gate.

Claim 13

An unlimited roll keyboard circuit, comprising: a. a keyboard having a plurality of switches therein, each switch being connected to a different key within the keyboard for sending out a one bit from each depressed key during each timing cycle; b. a first shift register, each of whose shift register cells is connected to a different switch of the keyboard, any depressed key in the keyboard causing the loading of a one bit in its associated shift register cell, at the strobe pulse during each timing cycle; c. a second shift register having the same number of shift register cells as the first shift register array, being connected to the output of the first shift register array, the second shift register serially receiving information out of the first shift register at each timing cycle; and d. a compare circuit means for comparing, during each timing cycle the binary bit out of the last cell of the first shift register with the binary bit out of the last cell of the second shift register allowing the compare circuit to send out a one bit when a one bit comes out of the first shift register and a zero binary bit, which is then inverted by an inverter, comes out of the second shift register during each timing cycle.

Claim 14

An unlimited roll keyboard circuit, comprising: a. a keyboard having a plurality of switches therein, each switch being connected to a different key within the keyboard for sending out a one bit from each depressed key during each timing cycle; b. a first shift register, each of whose shift register cells is connected to a different switch of the keyboard, any depressed key in the keyboard causing the loading of a one bit in its associated shift register cell, at the strobe pulse during each timing cycle; c. a second shift register having the same number of shift register cells as the first shift register array, being connected to the output of the first shift register array, the second shift register serially receiving information out of the first shift register at each timing cycle; and d. a compare circuit means for comparing, during each timing cycle the binary bit out of the last cell of the first shift register with the binary bit out of the last cell of the second shift register allowing the compare circuit to send out a one bit when a one bit comes out of the first shift register and a zero binary bit, which is then inverted by an inverter, comes out of the second shift register during each timing cycle.