Two channel read amplifier

Claim 2

A dual channel amplifier comprising: a first amplifying network; a second amplifying network coupled to said first amplifying network; an input means coupled to said first and second amplifying networks for selectively introducing electric signals to said first and second amplifying networks; an output means coupled to said first and second amplifying networks for selectively abstracting amplified electric signals from said first and second amplifying networks; a switching electric network coupled to said first and second amplifying networks for selectively switching said amplifying networks alternately between states wherein in one state said first amplifying network is operative, while said second amplifying network is non-operative and wheRein in the opposite state said first amplifying network is non-operative while said second amplifying network is operative; a first biasing means coupled to said switching electric network for providing bias to effect the switching between states of said amplifying networks; stabilizing circuit means coupled to said first and second amplifying networks for controlling the operating potential of said first and second networks whereby an operating point of said first and second networks is stabilized; and, a second biasing means coupled to said stabilizing circuit means for providing bias to said stabilizing circuit means.

Claim 3

A dual channel amplifier as recited in claim 1 wherein said switching electric network comprises a first transistor having a collector and having an emitter and base selectively coupled between said first biasing means and ground; a second transistor having a collector and also having an emitter and base selectively coupled between said first biasing means and ground; a first diode having an anode and cathode with said anode coupled to said collector of said first transistor and said cathode coupled to said input means; and, a second diode having an anode and cathode with said anode coupled to said collector of said second transistor and said cathode coupled to said input means.

Claim 4

A dual channel amplifier as recited in claim 2 wherein said transistor is a PNP transistor and said diode is a semiconductor diode.

Claim 5

A dual channel amplifier as recited in claim 2 including a first resistor coupled between said anode of said first diode and said collector of said first transistor; a second resistor coupled between said anode of said second diode and said collector of said second transistor; a first capacitor coupled between said collector of said first transistor and ground; and, a second capacitor coupled between said collector of said second transistor and ground.

Claim 6

A dual channel amplifier as recited in claim 2 wherein said first amplifying network comprises a first PNP transistor having a collector coupled to said second biasing means; an emitter coupled to said collector of said first transistor; a base coupled to said input means; a first NPN transistor having a base coupled to said collector of said first PNP transistor; an emitter coupled to said second biasing means; a collector coupled to said first biasing means: and wherein said second amplifying network comprises a second PNP transistor having a collector coupled to said second biasing means; an emitter coupled to said collector of said second transistor; a base coupled to said input means; a second NPN tranSistor having a base coupled to said collector of said second PNP transistor; an emitter coupled to said second biasing means; and, a collector coupled to said first biasing means.

Claim 7

A dual channel amplifier as recited in claim 5 including a first variable resistor coupled between said emitter of said first NPN transistor and said second biasing means for varying the gain of said first amplifying network; and, a second variable resistor coupled between said emitter of said second NPN transistor and said second biasinG means for varying the gain of said second amplifying network.

Claim 8

A dual channel amplifier as recited in claim 5 including a first RC network coupled to said first amplifying network for removing high frequency noise from said second amplifying network; and, a second RC network coupled to said second amplifying network for removing high frequency noise from said second amplifying network.

Claim 9

A dual channel amplifier as recited in claim 7 wherein said first RC network comprises a third resistor coupled between said anode of said first diode and said base of said first PNP transistor; a third capacitor coupled between said base of said first PNP transistor and ground; and wherein said second RC network comprIses a fourth resistor coupled between said anode of said second diode and said base of said second PNP transistor; and, a fourth capacitor coupled between said base of said second PNP transistor and ground.

Claim 10

In combination with the read-head of a tape transport device of a type used in a computer system and comprising in general capstan drives, a read-head, and reading and control circuits, a dual channel amplifier comprising: a. a first amplifying network; b. a second amplifying network coupled to said first amplifying network; c. an input means coupled to said first and second amplifying networks for selectively introducing electric signals to said first and second amplifying networks; d. an output means coupled to said first and second amplifying networks for selectively abstracting amplified signals from said first and said second amplifying networks; e. a switching electric network responsive to first bias signals, said switching network coupled to said first and second amplifying networks for selectively switching said networks alternately between states wherein in one state said first amplifying network is operative while said second amplifying network is non-operative, and where in the opposite state said first amplifying network is non-operative and said second amplifying network is operative; f. and, stabilizing circuit means coupled to said first and second amplifying networks said stabilizing circuit means responsive to second bias signals for controlling the operating potential of said first and second networks whereby unwanted oscillations in said first and second networks are eliminated.

Claim 11

In combination with the read-head of a tape transport device of a type used in a computer system and comprising in general capstan drives, a read-head, and reading and control circuits, a dual channel amplifier comprising: a. a first amplifying network; b. a second amplifying network coupled to said first amplifying network; c. an input means coupled to said first and second amplifying networks for selectively introducing electric signals to said first and second amplifying networks; d. an output means coupled to said first and second amplifying networks for selectively abstracting amplified signals from said first and said second amplifying networks; e. a switching electric network responsive to first bias signals, said switching network coupled to said first and second amplifying networks for selectively switching said networks alternately between states wherein in one state said first amplifying network is operative while said second amplifying network is non-operative, and where in the opposite state said first amplifying network is non-operative and said second amplifying network is operative; f. and, stabilizing circuit means coupled to said first and second amplifying networks said stabilizing circuit means responsive to second bias signals for controlling the operating potential of said first and second networks whereby unwanted oscillations in said first and second networks are eliminated.

Claim 12

A dual channel amplifier in combination with a read-head of a tape transport device as recited in claim 9 wherein said switching electric network comprises: a. a first transistor having a collector and having an emitter and base selectively coupled between said first biasing means and ground; b. a second transistor having a collector and also having an emitter and base selectively coupled between said first biasing means and ground; first diode having an anode and cathode with said anode coupled to said collector of said first transistor and said cathode coupled to said input means; and, d. a second diode having an anode and cathode with said anode coupled to said collector of said second transistor and said cathode coupled to said input means.

Claim 13

A dual channel amplifier as recited in claim 9 including stabilizing circuit meanS coupled to said first and second amplifying networks for providing compensating electric bias signals in response to unwanted electric signals when they appear on said first and said second amplifying networks for stabilizing the operating points of said first and second amplifying networks.

Claim 14

A dual channel amplifier comprising: a first amplifying network; a second amplifying network coupled to said first amplifying network; a single input means coupled to said first and second amplifying networks for selectively introducing different types of electric signals to said first and second amplifying networks; a single output means coupled to said first and second amplifying networks for selectively abstracting the amplified electric signals introduced at said input means; an electronic switching means coupled to said first and second amplifying networks said electronic switching means responsive to first bias signals for selectively switching said amplifying networks between states wherein in one state said first amplifying network is operative while said second amplifying network is inoperative, and wherein in the opposite state said first amplifying network is inoperative while said second amplifying network is operative; and operating - point stabilizing circuit means coupled to said first and second amplifying networks for stabilizing the operating potential of said first and second amplifying networks by controlling said operAting potential.

Claim 15

A dual channel amplifier comprising: a first amplifying network; a second amplifying network coupled to said first amplifying network; a single input means coupled to said first and second amplifying networks for selectively introducing different types of electric signals to said first and second amplifying networks; a single output means coupled to said first and second amplifying networks for selectively abstracting the amplified electric signals introduced at said input means; an electronic switching means coupled to said first and second amplifying networks said electronic switching means responsive to first bias signals for selectively switching said amplifying networks between states wherein in one state said first amplifying network is operative while said second amplifying network is inoperative, and wherein in the opposite state said first amplifying network is inoperative while said second amplifying network is operative; and operating - point stabilizing circuit means coupled to said first and second amplifying networks for stabilizing the operating potential of said first and second amplifying networks by controlling said operAting potential.

Claim 16

A dual channel amplifier as recited in claim 12 including variable gain circuit means coupled to said first and second amplifying networks for independently adjusting the gain of said first and second amplifying networks respectively.

Claim 17

A dual channel amplifier as recited in claim 12 including noise removing circuit means coupled to said first and second amplifying networks for removing high frequency noise from said amplifying networks.

Claim 18

A dual channel amplifier as recited in claim 12 wherein said operating-point stabilizing circuit means comprise a first stabilizing transistor and a second stabilizing transistor coupled to each other and to said first and second amplifying networks.

Claim 19

A dual channel amplifier as recited in claim 15 including automatic bias circuit means for providing stabilizing bias to said operating-point stabilizing circuit means for the stabilization of said first and second amplifying networks, said automatic bias circuit means comprising a first bias resistor and bias capacitor parallel coupled to said first stabilizing transistor, a second bias resistor and bias capacitor parallel coupled to said second stabilizing transistor, and a zener diode coupled to said second stabilizing transistor.

Claim 20

A dual channel amplifier comprising: a first amplifying network for optimally amplifying a first type of electronic signal; a second amplifying network for optimally amplifyinG a second type electronic signal; a single input means and a single output means coupled to said first and second amplifying networks for applying and abstracting electronic signals to and from said first and second amplifying networks respectively; electronic enabling means coupled to said first and second amplifying networks for selectively providing enabling signals to said first amplifying network in responSe to a first bias signal applied to said electronic enabling means while providing disabling signals to said second amplifying networks, and for selectively providing enabling signals to said second amplifying network in response to a second bias signal applied to said enabling means while providing disabling signals to said first amplifying network; and, stabilizing circuit means coupled to said first and second amplifying networks for controlling the operating potential of said first and second amplifying networks whereby an operating point of said first and second amplifying networks is controlled.

Claim 21

A dual channel amplifier comprising: a first amplifying network for optimally amplifying a first type of electronic signal; a second amplifying network for optimally amplifyinG a second type electronic signal; a single input means and a single output means coupled to said first and second amplifying networks for applying and abstracting electronic signals to and from said first and second amplifying networks respectively; electronic enabling means coupled to said first and second amplifying networks for selectively providing enabling signals to said first amplifying network in responSe to a first bias signal applied to said electronic enabling means while providing disabling signals to said second amplifying networks, and for selectively providing enabling signals to said second amplifying network in response to a second bias signal applied to said enabling means while providing disabling signals to said first amplifying network; and, stabilizing circuit means coupled to said first and second amplifying networks for controlling the operating potential of said first and second amplifying networks whereby an operating point of said first and second amplifying networks is controlled.

Claim 22

A dual channel amplifier as recited in claim 17 including RC circuit means coupled to said first and second amplifying networks for automatically eliminating high frequency noise in either enabled said first or second amplifying networks, and further including gain adjusting circuit means coupled to said first and second amplifying networks for independently varying the gain in either of said first or second amplifying networks.