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US3673501A
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Control logic for linear sequence generators and ring counters
Assignee: United States Department of the Navy
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Filing: 1971-08-18
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Granted: 1972-06-27
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Expires: 1991-08-18
Abstract
Abstract A control logic for linear sequence generators and ring counters to prevent ''''latch-up'''' in the ''''0'''' state having a linear sequence generator including a shift register with modulo-2 exclusive-OR feedback from the shift register to the shift register input and feedback through binary counters to detect and count n-1 consecutive ''''0''''s in the shift register to feed a ''''1'''' into the shift register to prevent ''''0'''' state latch, where n is the number of shift register stages used.
Inventors
- 👤 David L Zeph
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 07:35
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/84; G; G06; G06F; G06F7/00; G06F7/58; G06F7/582; G06F7/584; H03K21/00; H03K21/40; G06F2207/00; G06F2207/58; G06F2207/581; G06F2207/583
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
204 words
A control logic circuit for linear sequence generators and ring counters comprising: a shift register having a clock pulse input, a signal input, parallel entry inputs, a pulse enable input, and outputs; a feedback circuit through a plurality of exclusive-OR gates arranged in modulo-2 configuration from a preselected number of shift register outputs coupled to said shift register signal input to conduct only ''''1'''' states therethrough; a binary counter having a count enable parallel input, a count enable terminal input adapted to be coupled to a binary ''''1,'''' a clock pulse input, a pulse enable input, parallel entry inputs, and an output coupled to said shift register signal input; a clock pulse source coupled to said clock pulse inputs of said shift register and said binary counter; and gate circuits in said coupling between said exclusive-OR gates and said shift register signal input and between said binary counter and said shift register signal input whereby consecutive binary ''''0'''' inputs to said shift register until a single binary ''''1'''' appears through said exclusive-OR gates back to said shift register signal input and a count output of a binary ''''1'''' from said binary counter will prevent latch-up of said shift register in the binary ''''0'''' state.
Claim 2
Dependent Claim
204 words
A control logic circuit for linear sequence generators and ring counters comprising: a shift register having a clock pulse input, a signal input, parallel entry inputs, a pulse enable input, and outputs; a feedback circuit through a plurality of exclusive-OR gates arranged in modulo-2 configuration from a preselected number of shift register outputs coupled to said shift register signal input to conduct only ''''1'''' states therethrough; a binary counter having a count enable parallel input, a count enable terminal input adapted to be coupled to a binary ''''1,'''' a clock pulse input, a pulse enable input, parallel entry inputs, and an output coupled to said shift register signal input; a clock pulse source coupled to said clock pulse inputs of said shift register and said binary counter; and gate circuits in said coupling between said exclusive-OR gates and said shift register signal input and between said binary counter and said shift register signal input whereby consecutive binary ''''0'''' inputs to said shift register until a single binary ''''1'''' appears through said exclusive-OR gates back to said shift register signal input and a count output of a binary ''''1'''' from said binary counter will prevent latch-up of said shift register in the binary ''''0'''' state.
Claim 3
Dependent Claim
76 words
A control logic circuit as set forth in claim 1 wherein said gate circuits in said coupling between said exclusive-OR gate and said shift register signal input includes an OR-gate having the output of said exclusive-OR gate as one of its inputs and said output of said binary counter as a second input thereto, the output of said OR-gate constituting said signal input to said shift register and coupled to said binary counter pulse enable input.
Claim 4
Dependent Claim
26 words
A control logic circuit as set forth in claim 2 wherein said coupling between said OR-gate and said binary counter pulse enable input includes an inverter.
Claim 5
Dependent Claim
53 words
A control logic circuit as set forth in claim 1 wherein said gate circuits in said coupling between said exclusive-OR gate and said shift register signal input includes an OR-gate and NAND gates having outputs coupling the pulse enable inputs of said shift register and said binary counter to enable and disable same.
Claim 6
Dependent Claim
88 words
A control logic circuit as set forth in claim 4 wherein said NAND gates are two in number, one of which are one input coupled to the output of said exclusive-OR gate and a second input coupled to said output of said binary counter and the second NAND gate having one input coupled to the output of said one NAND gate and another input coupled to the output of said OR-gate, said OR-gate coupling the output of said binary counter to the signal input of said shift register.
Claim 7
Dependent Claim
42 words
A control logic circuit as set forth in claim 5 wherein said parallel entry inputs of said binary counter are adapted to be coupled to programming voltages and said parallel entry inputs of said shift register are coupled to a fixed potential.
Claim 8
Dependent Claim
138 words
A control logic circuit as set forth in claim 1 wherein said gate circuits in said coupling between said exclusive-OR gate and said shift register includes an OR-gate and two NAND gates, said OR-gate having one input coupled to the output Of said binary counter, a second input coupled to the output of said exclusive-OR gate, and an output coupled to the signal input of said shift register, one NAND gate having one input coupled to the output of said exclusive-OR gate, a second input coupled to the output of said binary counter, and the output thereof coupled to the pulse enable inputs of said shift register, and the other NAND gate having two inputs coupled in common to the output of said OR-gate and the output thereof coupled to the pulse enable inputs of said binary counter.
Claim 9
Dependent Claim
185 words
A control logic circuit as set forth in claim 1 wherein said gate circuits in said coupling between said exclusive-OR gates and said binary counter to said shift register signal input includes an OR-gate, two NAND gates, and a gate latch, said output of said binary counter being through one input of said OR-gate to said shift register signal input, the other input to said OR-gate being from said exclusive-OR gate in common through one of said two NAND gates to said gate latch, the output of said gate latch being in common to said count enable parallel inputs of said binary counter, to said parallel enable inputs of said shift register, and to one input of the other of said two NAND gates, the second input to said other of said two NAND gates coupled to the output of said OR-gate, and the output of said other of said two NAND gates being coupled to said pulse enable inputs of said binary counter to latch up counting by said binary counter and shift register until a restart signal is applied to said gate latch.
Claim 10
Dependent Claim
44 words
A control logic circuit as set forth in claim 8 wherein said gate latch comprises a pair of cross-coupled NAND gates having a restarting input to one and having said output of one of said two NAND gates to the other of said pair.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-06-27 | 1975-12-27 | 1976-06-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-06-27 | 1979-12-27 | 1980-06-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-06-27 | 1983-12-27 | 1984-06-27 | $7700.00 | Window Closed / Lapsed |