Noise immune flip-flop circuit arrangement

Claim 2

A transition triggered flip-flop circuit comprising a data input means and at least one output means, a clocking input means, a first capacitor and a first resistor connected in series across a voltage source, said clocking input means being connected to a first junction between said first capacitor and said first resistor, a first logic circuit means having at least two input terminals and an output terminal, said output terminal being coupled to said first junction, said input terminals being coupled to an output terminal of a second logic circuit means having two input terminals one of which is coupled to an output terminal of a third logic circuit means and the other of which is coupled to a second junction between a second capacitor and a resistor, said second capacitor and said second resistor being connected in series across a voltage source, said third logic circuit means having one input terminal connected to a source of potential and a second input terminal coupled to an output terminal of a fourth logic circuit means via a third capacitor and to a point of reference potential via a third resistor, the output terminal of said fourth logic circuit means being connected to said second junction and said fourth logic circuit means having at least two input terminals.

Claim 3

A circuit as claimed in claim 1 wherein each of said logic circuit means comprises respective individual NAND circuit means.

Claim 4

In a transition triggered flip-flop circuit having a data input means and at least one output means, a clocking input means, a first capacitor and a first resistor connected in series across a voltage source, said clocking input means being connected to a junction between said first capacitor and said first resistor, and NAND circuit means coupled to said junction for controlling the charging and discharging of said first capacitor, said NAND circuit means comprising a first NAND circuit having at least two input terminals and an output terminal, said output terminal being coupled to said first junction, said input terminals being coupled to an output terminal of a second NAND circuit having two input terminals one of which is coupled to an output terminal of a third NAND circuit and the other of which is coupled to a second junction between a second capacitor and a resistor, said second capacitor and said second resistor being connected in series across a voltage source, said third NAND circuit having one input terminal connected to a source of potential and a second input terminal coupled to an output terminal of a fourth NAND circuit via a third capacitor and to a point of reference potential via a third resistor, the output terminal of said fourth NAND circuit being connected to said second junction and said fourth NAND circuit having at least two input terminals.

Claim 5

In a transition triggered flip-flop circuit having a data input means and at least one output means, a clocking input means, a first capacitor and a first resistor connected in series across a voltage source, said clocking input means being connected to a junction between said first capacitor and said first resistor, and NAND circuit means coupled to said junction for controlling the charging and discharging of said first capacitor, said NAND circuit means comprising a first NAND circuit having at least two input terminals and an output terminal, said output terminal being coupled to said first junction, said input terminals being coupled to an output terminal of a second NAND circuit having two input terminals one of which is coupled to an output terminal of a third NAND circuit and the other of which is coupled to a second junction between a second capacitor and a resistor, said second capacitor and said second resistor being connected in series across a voltage source, said third NAND circuit having one input terminal connected to a source of potential and a second input terminal coupled to an output terminal of a fourth NAND circuit via a third capacitor and to a point of reference potential via a third resistor, the output terminal of said fourth NAND circuit being connected to said second junction and said fourth NAND circuit having at least two input terminals.

Claim 6

A circuit as claimed in claim 3 wherein a diode is connected between the output terminal of said first NAND circuit and said first junction.

Claim 7

A circuit as claimed in claim 3 wherein a diode is connected between the output terminal of said fourth NAND circuit and said second junction.

Claim 8

A circuit as claimed in claim 3 wherein a diode is connected across said third resistor.

Claim 9

A circuit as claimed in claim 3 wherein a first diode is connected between the output terminal of said first NAND circuit and said first junction, a second diode is connected between the output terminal of said fourth NAND circuit and said second junction, and a third diode is connected across said third resistor.

Claim 10

In a transition triggered flip-flop circuit having a setting input means and a clearing input means which produces a clearing signal output only in response to a clearing signal pulse input thereto having at least a predetermined pulse width, said clearing input means comprising a first NAND circuit having an output terminal coupled to said clearing input means and to a source of potential via a first resistor, said first NAND circuit having one input terminal coupled to a source of potential and a second input terminal connected to a junction between a second resistor and a capacitor, said second resistor and said capacitor being connected in series across a voltage source, and a second NAND circuit having an output terminal coupled to said junction, said second NAND circuit having at least two input terminals at least one of which receives said clearing signal pulse input whereby said clearing signal output is produced only when said clearing signal pulse input exceeds said predetermined width.

Claim 11

In a transition triggered flip-flop circuit having a setting input means and a clearing input means which produces a clearing signal output only in response to a clearing signal pulse input thereto having at least a predetermined pulse width, said clearing input means comprising a first NAND circuit having an output terminal coupled to said clearing input means and to a source of potential via a first resistor, said first NAND circuit having one input terminal coupled to a source of potential and a second input terminal connected to a junction between a second resistor and a capacitor, said second resistor and said capacitor being connected in series across a voltage source, and a second NAND circuit having an output terminal coupled to said junction, said second NAND circuit having at least two input terminals at least one of which receives said clearing signal pulse input whereby said clearing signal output is produced only when said clearing signal pulse input exceeds said predetermined width.

Claim 12

In a triggered flip-flop circuit having at least one data input and at least one clocking input, at least a first output terminal and a second output terminal, said first output terminal being coupled to the input terminals of a first logic circuit means, said second output terminal being coupled to the input terminals of a second logic circuit means, an output terminal of said first logic circuit means being coupled to a voltage source via a first resistor and a diode, and an output terminal of said second logic circuit means being coupled to said voltage source via a second resistor and said diode, a capacitor connected across said voltage source and to one electrode of said diode, the other electrode of said diode being connected to a first end of each of said first and second resistors, a second end of each of said resistors being connected respectively to the output terminal of said first logic circuit means and the output terminal of said second logic circuit means whereby the two logic circuit means are energized from the same voltage source.

Claim 13

In a triggered flip-flop circuit having at least one data input and at least one clocking input, at least a first output terminal and a second output terminal, said first output terminal being coupled to the input terminals of a first logic circuit means, said second output terminal being coupled to the input terminals of a second logic circuit means, an output terminal of said first logic circuit means being coupled to a voltage source via a first resistor and a diode, and an output terminal of said second logic circuit means being coupled to said voltage source via a second resistor and said diode, a capacitor connected across said voltage source and to one electrode of said diode, the other electrode of said diode being connected to a first end of each of said first and second resistors, a second end of each of said resistors being connected respectively to the output terminal of said first logic circuit means and the output terminal of said second logic circuit means whereby the two logic circuit means are energized from the same voltage source.

Claim 14

A circuit according to claim 9 wherein said first logic circuit means and said second logic circuIt means are respectively a first NAND circuit and a second NAND circuit.

Claim 15

In a transition triggered flip-flop circuit having a data input and at least one output, a clocking input means including first time constant means and first NAND circuit means for triggering said flip-flop in response to the occurrence of clock pulses having a width at least of a given predetermined width, and a clearing input means including second time constant means and a second NAND circuit means for clearing said flip-flop in response to the occurrence of clearing pulses having a width of at least a given predetermined width, whereby said flip-flop circuit is immune to pulses on its clocking input and on its clearing input which have widths less than the respective predetermined widths.

Claim 16

In a transition triggered flip-flop circuit having a data input and at least one output, a clocking input means including first time constant means and first NAND circuit means for triggering said flip-flop in response to the occurrence of clock pulses having a width at least of a given predetermined width, and a clearing input means including second time constant means and a second NAND circuit means for clearing said flip-flop in response to the occurrence of clearing pulses having a width of at least a given predetermined width, whereby said flip-flop circuit is immune to pulses on its clocking input and on its clearing input which have widths less than the respective predetermined widths.

Claim 17

The circuit as claimed in claim 11 wherein said circuit has at least two output terminals, said first output terminal being coupled to the input terminals of a third NAND circuit and said second output terminal being coupled to the input terminals of a fourth NAND circuit.

Claim 18

In a transition triggered flip-flop circuit, a data input means, at least one output means, a setting input means, and time constant means and NAND circuit means coupled to said setting input means for applying a clearing input signal thereto having a width at least of a given predetermined width, whereby the flip-flop circuit may be set only by a setting signal having a width substantially equal to or greater than said predetermined width.

Claim 19

In a transition triggered flip-flop circuit, a data input means, at least one output means, a setting input means, and time constant means and NAND circuit means coupled to said setting input means for applying a clearing input signal thereto having a width at least of a given predetermined width, whereby the flip-flop circuit may be set only by a setting signal having a width substantially equal to or greater than said predetermined width.

Claim 20

A circuit as claimed in claim 13 wherein said time constant means and said NAND circuit means comprises a first NAND circuit having an output terminal coupled to said setting input means and to a source of potential via a first resistor, said first NAND circuit having one input terminal coupled to a source of potential and a second input terminal connected to a junction between a second resistor and a capacitor, said second resistor and said capacitor being connected in series across a voltage source, and a second NAND circuit having an output terminal coupled to said junction, said second NAND circuit having at least two input terminals.