Pseudo-and gate having failsafe qualities

Claim 1

For use in combination with a logic organization employing a logic information signal which is alternatively of TRUE and UNTRUE states, a failsafe circuit for detecting simultaneous presence of a TRUE signal at two or more logic signal inputs, comprising: a sequence of two or more serially connected flip-flop stages operatively interconneCted to form a pulse frequency division network of the type employing a mode of operation involving propagation of state changes through the sequence of stages, said frequency division network being operative to receive a pulse frequency at its input and to produce at its output the pulse frequency divided by a factor of N, where N is an integer equal to the number of flip-flop stages, each of the flip-flop stages of the sequence being of the master-slave type construction which includes an arrangement of two active amplification and switching devices which are regeneratively cross-coupled by direct current cross-coupling paths, each of the flip-flop stages of the sequence being operative to change state only during application of a predetermined operating potential to the arrangement of two active devices, a corresponding sequence of two or more logic signal input networks, the logic signal input networks each including a circuit means for adapting said TRUE signal as said predetermined operating potential and for individually applying same to the active device arrangement of the corresponding flip-flop stage of the sequence of flip-flop stages, a signal source means for pulsing the pulse frequency division network with a signal of predetermined pulse frequency, FREQin, said predetermined pulse frequency being substantially higher than the maximum normal rate of change of logic state of the signals to be applied to the logic signal input networks, and frequency selective circuit means for detecting a signal frequency, FREQin divided by N, at the output of the last flip-flop stage and for producing an output signal representing a TRUE output state of the psuedo-AND gate in response thereto.