Four phase encoder system for three frequency modulation

Claim 2

An improved encoder for translating an input NRZ data waveform into a self-clocking three frequency waveform using a first phase signal having pulses which occur only at the boundaries of the bit intervals of said data waveform and second and third phase signals each having pulses which occur only at successive predetermined times within said bit intervals, said encoder comprising: a clocked bistable storage device, including a CLOCK input for receiving said third phase signal and a DATA input for receiving said input NRZ waveform, said storage device being conditioned by the pulses of said third phase signal to produce a pair of complementary data signals, each being delayed by a portion of one bit interval to said input NRZ waveform; a first gate connected to receive a predetermined one of said complementary data signals, the complement of said NRZ waveform and the pulses of said second phase signal, said first gate being enabled to pass pulses of said second phase signal when said predetermined one of the data signals and said complement of NRZ waveform are in the same state representative of successive binary ZERO bits in said input NRZ waveform; a second gate connected to receive said NRZ waveform and said third phase signal, said second gate being enabled to pass pulses of said third phase signal when said NRZ waveform is in a state representative of a binary ONE bit in said NRZ waveform; a third gate connected to receive the pulse outputs of said first and second gate; and, a complementing output flip-flop connected to said third gate and being conditioned by said pulses to produce said three frequency waveform in which transitions occur at the center of a binary ONE bit and between successive binary ZERO bits.

Claim 3

The encoder of claim 1 wherein the pulses of said second and third phase signals occur respectively at one quarter and three quarters of said bit interval.

Claim 4

The encoder of claim 1 wherein said flip-flops are of the D type.

Claim 5

The encoder of claim 1 wherein said all of said gates are NAND gates.

Claim 6

An encoder for translating bits of a NRZ data input signal into a self-clocking waveform comprising: a multiphase clock for generating pulses of a plurality of phases, said plurality including a succession of at least first, second, and third phase waveforms having predetermined phase relationships to one another; means for synchronizing the clocking of said NRZ signal with said first phase waveform of said clock so that the pulses of said first phAse waveform occur at the boundaries between successive bit intervals of said NRZ signal and the pulses of the other of said phase waveforms occur within said bit intervals; a clocked flip-flop having a CLOCK input connected to receive said third phase waveform and a DATA input to receive said NRZ signal, said flip-flop being conditioned by the pulses of said third phase waveform to produce a data signal and the complement of said data signal by delaying said NRZ signal a portion of said bit interval; first gating means coupled to said clocked flip-flop for receiving said complement of said data signal, said NRZ signal and the pulses of said third phase waveform, said first gating means being conditioned to pass pulses of said third phase waveform when said data signal and said NRZ signal are in a first state representative of the occurrence of successive binary ZERO bits in said NRZ signal; second gating means connected to receive pulses of said second phase waveform and said NRZ signal, said second gating means being conditioned to pass pulses of said third phase waveform when said NRZ signal is in a state representative of said bits being binary ONES; third gating means coupled to said first and second gating means for receiving pulses of said second and third phase waveforms; and a complementing output flip-flop coupled to said third gating means and being conditioned by said pulses of said second and third phase waveforms to produce said self-clocking waveform in which transitions occur at the center of a binary ONE bit and between successive binary ZERO bits.

Claim 7

An encoder for translating bits of a NRZ data input signal into a self-clocking waveform comprising: a multiphase clock for generating pulses of a plurality of phases, said plurality including a succession of at least first, second, and third phase waveforms having predetermined phase relationships to one another; means for synchronizing the clocking of said NRZ signal with said first phase waveform of said clock so that the pulses of said first phAse waveform occur at the boundaries between successive bit intervals of said NRZ signal and the pulses of the other of said phase waveforms occur within said bit intervals; a clocked flip-flop having a CLOCK input connected to receive said third phase waveform and a DATA input to receive said NRZ signal, said flip-flop being conditioned by the pulses of said third phase waveform to produce a data signal and the complement of said data signal by delaying said NRZ signal a portion of said bit interval; first gating means coupled to said clocked flip-flop for receiving said complement of said data signal, said NRZ signal and the pulses of said third phase waveform, said first gating means being conditioned to pass pulses of said third phase waveform when said data signal and said NRZ signal are in a first state representative of the occurrence of successive binary ZERO bits in said NRZ signal; second gating means connected to receive pulses of said second phase waveform and said NRZ signal, said second gating means being conditioned to pass pulses of said third phase waveform when said NRZ signal is in a state representative of said bits being binary ONES; third gating means coupled to said first and second gating means for receiving pulses of said second and third phase waveforms; and a complementing output flip-flop coupled to said third gating means and being conditioned by said pulses of said second and third phase waveforms to produce said self-clocking waveform in which transitions occur at the center of a binary ONE bit and between successive binary ZERO bits.

Claim 8

The encoder of claim 5 wherein said flip-flops are of the D type and said pulses of said second and third phase waveforms respectively occur at a time corresponding to one quarter and three quarters of said bit interval.

Claim 9

The encoder of claim 5 wherein said gates are NAND gates.

Claim 10

The encoder of claim 5 wherein said multiphase clock includes a plurality of flip-flops connected in series to form a shift register, gating means for connecting the outputs of a predetermined number of said flip-flops to form a recirculating input to said shift register, said clock further including a set of gating means having a plurality of gates corresponding in number to said phases and being connected to predetermined ones of said flip-flops for deriving pulses of said first, second and third phases.

Claim 11

The encoder of claim 5 wherein said synchronizing means includes a data shift register connected to have its contents shifted by pulses of said first one of said phases to establish said predetermined phase relationship between said bits and the pulses of said first, second, and third phases.

Claim 12

The encoder of claim 8 wherein said flip-flops are of the D type.

Claim 13

The encoder of claim 8 wherein said gating means includes a NOR gate and said plurality of gates are NAND gates.

Claim 14

An encoder for translating bits of a data stream waveform, W, into a three frequency self-clocking waveform comprising: a four phase clock generator for generating pulses of at least first, second, and third phases ( phi 1), ( phi 2), and ( phi 4) in response to a clock input signal so as to have said ( phi 1) pulses coincide with the boundaries of said bits and said ( phi 2) and ( phi 4) pulses each coincide with different predetermined portions of said bits; a clocked bistable device including a CLOCK input for receiving said ( phi 4) pulses and a DATA input for receiving said data stream waveform, (W), said bistable device being conditioned to be switched by said ( phi 4) pulses to produce a data signal, (W1) and its complement (W1), each delayed by a portion of a bit interval to said waveform (W); a first gate for receiving the complement of said data waveform (W), said complement (W1) and said ( phi 2) pulses, said gate being enabled to produce a pulse output (F1) in accordance with the expression: (F1 W.W1. phi 2); a second gate for receiving said data waveform (W) and said ( phi 4) pulses, said gate being enabled to produce a pulse output (F2) as defined by the relationship: (F2 W. phi 4); and, a complementing output bistable device including a gate connected to receive said outputs (F1) and (F2), said gate being enabled to produce an output (F3) in accordance with the relationship: (F3 F1+F2) for conditioning said bistable device to switch state during a bit interval when there is a binary ONE and between bit intervals when there are two successive binary ZEROS in said data stream waveform.

Claim 15

An encoder for translating bits of a data stream waveform, W, into a three frequency self-clocking waveform comprising: a four phase clock generator for generating pulses of at least first, second, and third phases ( phi 1), ( phi 2), and ( phi 4) in response to a clock input signal so as to have said ( phi 1) pulses coincide with the boundaries of said bits and said ( phi 2) and ( phi 4) pulses each coincide with different predetermined portions of said bits; a clocked bistable device including a CLOCK input for receiving said ( phi 4) pulses and a DATA input for receiving said data stream waveform, (W), said bistable device being conditioned to be switched by said ( phi 4) pulses to produce a data signal, (W1) and its complement (W1), each delayed by a portion of a bit interval to said waveform (W); a first gate for receiving the complement of said data waveform (W), said complement (W1) and said ( phi 2) pulses, said gate being enabled to produce a pulse output (F1) in accordance with the expression: (F1 W.W1. phi 2); a second gate for receiving said data waveform (W) and said ( phi 4) pulses, said gate being enabled to produce a pulse output (F2) as defined by the relationship: (F2 W. phi 4); and, a complementing output bistable device including a gate connected to receive said outputs (F1) and (F2), said gate being enabled to produce an output (F3) in accordance with the relationship: (F3 F1+F2) for conditioning said bistable device to switch state during a bit interval when there is a binary ONE and between bit intervals when there are two successive binary ZEROS in said data stream waveform.

Claim 16

The encoder of claim 12 wherein said storage devices are D type flip-flops and said gates are NAND gates.

Claim 17

The encoder of claim 12 further including a data shift register connected to receive said ( phi 1) pulses and being conditioned thereby to apply the bits of said data stream waveform to said DATA input so as to establish said coincidences between each of said pulses and said bits.

Claim 18

The encoder of claim 12 wherein said four phase clock includes a plurality of flip-flops (X1), (X2), (X3), and (X4) connected in series to form a shift register, each of said flip-flops having a CLOCK input and a DATA input, a gate connected to receive outputs of said flip-flops (X1), (X2), and (X4) and to apply an output (F) to the DATA input of said flip-flop (X1), said gate being enabled to produce said (F) output in accordance with the relationship: (F X1.X2.X3), said clock further including a set of gates, each being connected to a different one of said flip-flops (X1), (X2), and (X4) and to receive said clock input signal for deriving said ( phi 1), ( phi 2), and ( phi 4) pulses.

Claim 19

The encoder of claim 15 wherein phi 2 and phi 4 pulses occur respectively at one quarter and three quarters of said bit intervals.

Claim 20

The encoder of claim 15 wherein said flip-flops are of the D type.

Claim 21

The encoder of claim 15 wherein said gate is a NOR gate and said set of gates are NAND gates.