Patent US3671946A successfully refreshed from Google Patents.
US3671946A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Binary storage circuit arrangement
Assignee: US Philips Corp
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Filing: 1970-05-04
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Granted: 1972-06-20
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Expires: 1990-05-04
Abstract
Abstract The invention relates to a bistable trigger circuit comprising two transistors and associated with a group of trigger circuits which may be not only in two binary information states in which one transistor is conducting and the other is cut off, but also in a rest position of low dissipation or in a state of higher dissipation for writing or reading information. According to the invention the trigger circuits can be passed individually into the state of higher dissipation by means of two further transistors, the emitters of which are connected to a control-point individually associated with the triggers and the collectors of which are connected to the respective collectors of the two first transistors, in which write signals are applied to the bases of the further transistors.
Inventors
- 👤 Einar Andreas Aagaard
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 17:31
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/411; G11C11/4116; G11C11/413; G11C11/414; G11C11/415; G11C8/00; G11C8/16; H; H03; H03K; H03K3/00; H03K3/01; H03K3/012
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
318 words
A binary storage element for a group of trigger circuits, each element comprising a first transistor having a base, a collector, and an emitter, a second transistor having a base, a collector, and an emitter, means for cross coupling the bases and collectors of the first and second transistors, whereby the first and second transistors comprise a trigger circuit wherein one of the transistors is conducting and the other is cut off, a third transistor having a base, a collector and an emitter, a fourth transistor having a base, a collector, and an emitter, means for connecting the collector of the first transistor to the collector of the third transistor, means for connecting the collector of the second transistor to the collector of the fourth transistor, means for connecting the base of the third transistor to a first write conductor, means for connecting the base of the fourth transistor to a second write conductor, means for connecting the first and second writE conductors to the bases of corresponding third and fourth transistors of other circuit elements in the group of trigger circuits, means for connecting emitters of the four transistors in each element to a common identifying point, the identifying point comprising means for selectively providing a first and a second potential, the first potential having a value sufficient to maintain the trigger in a rest position of low power dissipation wherein alteration of the conductive state of the trigger is prevented, the second potential having a value sufficient to enable the trigger to switch conductive states of the first and second transistors in response to a signal on the first or second write conductor, means for controlling the potential of the first and second potential providing means, the first and second transistors each having a further emitter, and means for connecting the further emitters of the first and second transistors to a common point of constant potential.
Claim 2
Dependent Claim
318 words
A binary storage element for a group of trigger circuits, each element comprising a first transistor having a base, a collector, and an emitter, a second transistor having a base, a collector, and an emitter, means for cross coupling the bases and collectors of the first and second transistors, whereby the first and second transistors comprise a trigger circuit wherein one of the transistors is conducting and the other is cut off, a third transistor having a base, a collector and an emitter, a fourth transistor having a base, a collector, and an emitter, means for connecting the collector of the first transistor to the collector of the third transistor, means for connecting the collector of the second transistor to the collector of the fourth transistor, means for connecting the base of the third transistor to a first write conductor, means for connecting the base of the fourth transistor to a second write conductor, means for connecting the first and second writE conductors to the bases of corresponding third and fourth transistors of other circuit elements in the group of trigger circuits, means for connecting emitters of the four transistors in each element to a common identifying point, the identifying point comprising means for selectively providing a first and a second potential, the first potential having a value sufficient to maintain the trigger in a rest position of low power dissipation wherein alteration of the conductive state of the trigger is prevented, the second potential having a value sufficient to enable the trigger to switch conductive states of the first and second transistors in response to a signal on the first or second write conductor, means for controlling the potential of the first and second potential providing means, the first and second transistors each having a further emitter, and means for connecting the further emitters of the first and second transistors to a common point of constant potential.
Claim 3
Dependent Claim
95 words
A storage arrangement as claimed in claim 1 wherein the collector of at least the first transistor of the trigger is connected to a read gate constructed as an or-gate with a plurality of control-inputs connected each to the collectors of the first and third transistors of different trigger circuits, the output of the gate being connected to a read conductor common to the group of triggers so that, if the first transistor is highly conducting the threshold of the gate input concerned is exceeded and a read signal is applied to the read conductor.
Claim 4
Dependent Claim
44 words
A storage arrangement as claimed in claim 2 wherein the or-gate is constructed as a multi-emitter transistor, the various emitters of which form the control-inputs, the collector being connected to a read conductor and the base being connected to a point of constant potential.
Claim 5
Dependent Claim
58 words
A storage arrangement as claimed in claim 3 wherein also the collectors of the second and fourth transistors of a number of trigger circuits are connected to different emitters of a multi-emitter transistor, the collector of which is connected to a second common read conductor and the base of which is connected to the point of constant potential.
Claim 6
Dependent Claim
32 words
A storage arrangement as claimed in claim 3 wherein the collectors of the second and fourth transistors of the trigger circuits are connected via a diode to the point of constant potential.
Claim 7
Dependent Claim
41 words
A storage arrangement as claimed in claim 2 wherein the read and write conductors are pairwise combined and the base electrodes of the third and fourth transistors are connected via at least one diode to the read and write conductor concerned.
Claim 8
Dependent Claim
25 words
A storage arrangement as claimed in claim 6 wherein the diodes are constructed in the form of second emitters of the third and fourth transistors.
Claim 9
Dependent Claim
122 words
A storage arrangement as claimed in claim 1 wherein a number of switching transistors are arranged in the rows and columns of a matrix, while the bases of the transistors of one and the same row are connected to the same row control-conductor and the emitters of transistors of one and the same column are connected to the same column control-conductor, and the collectors of the transistors are connected to the individual identifying points of the various trigger circuits, there being provided means for applying a current or voltage pulse to one column control-conductor and one row control-conductor so that the switching transistor concerned becomes conductive and the trigger circuit connected to the collector thereof gets into the state of high dissipation.
References Cited (Backward Citations)
US3292008A
Cited
US3309534A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-06-20 | 1975-12-20 | 1976-06-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-06-20 | 1979-12-20 | 1980-06-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-06-20 | 1983-12-20 | 1984-06-20 | $7700.00 | Window Closed / Lapsed |