A calculator for a multiprocessor system

Claim 2

In a multiprocessor computer arrangement having a plurality of modules each being under control of a common central control means which provides identical control signals to all of the modules, a function calculator unit for each module for selectively altering the respective module response to said control signals comprising: a. product forming means for performing an arithmetic product operation on binary signals connected sequentially to an input thereof in response to a first set of said control signals, b. means connected to each one of a plurality of operational circuits which comprise the module for selectively coupling functional signals indicative of the state of each of said operational circuits and generated thereby to said input of said product forming means in sequence as directed by a second set of said control signals, and c. summing logic means connected to said product logic means for carrying out an arithmetic sum operation on consecutive signals on the signal output of said product forming means in response to a third set of said control signals, wherein said central control means is programmable to generate said first, second and third sets of control signals in any quantity and in any order to obtain the arithmetic sum of products of program selected function signals to condition the response of the module to subsequently received control signals.

Claim 3

The invention recited in claim 1 wherein said coupling means incorporates complementing means for selectively inverting functional signals prior to coupling such signals to said input of said product forming means as directed by a unique set of control signals.

Claim 4

The invention recited in claim 1 wherein said product forming means includes an AND gate and binary storage means whose output is connected to an input of said AND gate, and wherein said storage means is arranged to store the last arithmetic product formed as directed by a last received one of said first set of control signals.

Claim 5

The invention recited in claim 3 wherein said summing logic means comprises an OR gate having one input connected to said binary storage means, and a bistable device having an input connected to an output of said OR gate and an output thereof connected to another input of said OR gate, and wherein the signal present at the output of said bistable device conditions the response of said module to subsequently received control signals.

Claim 6

In a computer system including a plurality of processing elements each being under control of a central control means which provides control signals simultaneously to all the processing elements; each of said processors including means connected to said control signals for decoding said signals to determine individual element processing signals; means interconnecting individual processing elements for transmitting data as directed by said control signals; and a function calculator for each said processing element comprising, a multiplexor for sequentially connecting an output signal from any one of a plurality of operational subcircuits which comprise each particular processing element to said calculator, said multiplexor being operative in response to a first set of control signals, a complement variable circuit connected to said multiplexor for receiving the output signal therefrom and responsive to a second set of control signals for forming the complement of said output signals as directed, AND function means including an AND gate and a bistable device serially connected, an input of said AND gate being connected to the output of said complement variable means, said AND function means being arranged to form the arithmetic product of consecutive ones of said output signals as received from said complement variable means in response to a third set of control signals, OR function means connected to the output of said AND function means including an OR gate serially connected to a second bistable device, and said OR function means being arranged to form the arithmetic sum of the output signal of said AND function means.

Claim 7

In a computer system including a plurality of processing elements each being under control of a central control means which provides control signals simultaneously to all the processing elements; each of said processors including means connected to said control signals for decoding said signals to determine individual element processing signals; means interconnecting individual processing elements for transmitting data as directed by said control signals; and a function calculator for each said processing element comprising, a multiplexor for sequentially connecting an output signal from any one of a plurality of operational subcircuits which comprise each particular processing element to said calculator, said multiplexor being operative in response to a first set of control signals, a complement variable circuit connected to said multiplexor for receiving the output signal therefrom and responsive to a second set of control signals for forming the complement of said output signals as directed, AND function means including an AND gate and a bistable device serially connected, an input of said AND gate being connected to the output of said complement variable means, said AND function means being arranged to form the arithmetic product of consecutive ones of said output signals as received from said complement variable means in response to a third set of control signals, OR function means connected to the output of said AND function means including an OR gate serially connected to a second bistable device, and said OR function means being arranged to form the arithmetic sum of the output signal of said AND function means.