Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
126 words
A circuit for generating timing pulses for a receiver system constantly synchronized with transmission pulses of a transmitter system, comprising: a pulse generator; a counter connected to said pulse generator and having adjustable initial and final count values and operable to count the generated pulses; a memory; means for receiving transmission pulses operable to transfer pulse count from said counter to said memory upon receipt of a transmission pulse; a final value computer connected to said memory for computing the deviation of the momentary pulse count from a predetermined final pulse count; comparison means connected between said computer and said counter for generating an output timing pulse which resets said counter to its initial value upon equality between the contents of said computer and said counter.
Claim 2
Dependent Claim
126 words
A circuit for generating timing pulses for a receiver system constantly synchronized with transmission pulses of a transmitter system, comprising: a pulse generator; a counter connected to said pulse generator and having adjustable initial and final count values and operable to count the generated pulses; a memory; means for receiving transmission pulses operable to transfer pulse count from said counter to said memory upon receipt of a transmission pulse; a final value computer connected to said memory for computing the deviation of the momentary pulse count from a predetermined final pulse count; comparison means connected between said computer and said counter for generating an output timing pulse which resets said counter to its initial value upon equality between the contents of said computer and said counter.
Claim 3
Dependent Claim
29 words
The circuit of claim 1, wherein said pulse generator includes means for generating pulses to be counted at a rate of at least twice that of the transmission pulses.
Claim 4
Dependent Claim
27 words
The circuit of claim 1, wherein said receiving means includes switching means interposed between said counter and said memory and operated in response to a transmission pulse.
Claim 5
Dependent Claim
56 words
The circuit of claim 1, wherein said computer operates to compute in accordance with the expression EN EO + Alpha (ZN - ZO) where EN is the final count value of the counter, EO the initial count value of the counter, Alpha a proportionality constant, ZN the instantaneous count value, and ZO the predetermined count value.
Claim 6
Dependent Claim
23 words
The circuit of claim 4, comprising means for establishing the initial and final values of said counter symmetrically about the predetermined count ZO.
Claim 7
Dependent Claim
44 words
The circuit of claim 1, comprising an initial value computer connected to said memory and to said counter for computing and supplying to said counter the initial value as a function of the deviation of the momentary count value from the predetermined count value.
Claim 8
Dependent Claim
33 words
The circuit of claim 6, wherein said receiving means includes a switch interposed between said counter and said memory and operable to transfer the pulse count therebetween upon receipt of a transmission pulse.
Claim 9
Dependent Claim
48 words
The circuit of claim 6, wherein said computer includes means for computing the initial value in accordance with the expression AN 1 AO + Beta (ZN - ZO) Where AO is the initial value, Beta is a proportionality constant and AN 1 is the new computed initial value.
Claim 10
Dependent Claim
33 words
The circuit of claim 8, wherein said final value computer includes means for computing the final value in accordance with the expression EN EO + ( Alpha + Beta ) (ZN - ZO).
Claim 11
Dependent Claim
21 words
The circuit of claim 9, wherein said final value computer includes means which establishes the relationship Beta 1 - Alpha /2.
Claim 12
Dependent Claim
26 words
The circuit of claim 10, comprising a smoothing member connected in said circuit for preventing minor phase deviations due to minor deviations of the transmission impulses.
Claim 13
Dependent Claim
52 words
The circuit of claim 11, wherein said smoothing member comprises a divider connected between said memory and said final value computer, a multiplier connected to said divider, a subtractor connected to said divider and to said multiplier, and an adder connected to said counter, to said subtractor and to said receiving means.