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Patent US3671871A successfully refreshed from Google Patents.
US3671871A
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Signal frequency synthesizer
Assignee: Northrop Grumman Corp
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Filing: 1970-12-14
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Granted: 1972-06-20
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Expires: 1990-12-14
Abstract
Abstract A plurality of binary related anti-coincident pulse trains which are precisely related in frequency and phase to a reference frequency are generated in a binary rate multiplier. The rate multiplier includes gating and control circuitry whereby predetermined combinations of these pulse trains are selectively summed together to provide various output frequencies. The output of the binary rate multiplier, which comprises square wave signals having a predetermined frequency relative to the reference signal frequency, are divided to minimize the effects of irregularities in the frequency of the multiplier output and to provide square waves having substantially uniform periods. These square waves are then appropriately gated and filtered to produce quadrature related sine waves.
Inventors
- 👤 Robert E Malm
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 15:30
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/60; G06F7/68
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
158 words
A signal frequency synthesizer for selectively providing an output signal at any one of a plurality of frequencies, comprising: a reference signal source, means for generating a plurality of binary related pulse trains which are in anti-coincidence and the frequencies of which have a predetermined fixed relationship with the frequency of said reference signal source, means for selectively adding together any desired combination of said binary related pulse trains, first and second frequency divider means for dividing the frequency of said added pulse trains, means responsive to the outputs of said divider means for alternately gating a number of pulses corresponding to the dividing factor of said divider means from the output of said means for generating binary-related pulse trains to the inputs of each of said divider means in turn, and first and second means responsive to the outputs of said first and second frequency divider means respectively for generating quadrature related square waves in accordance therewith.
Claim 2
Dependent Claim
158 words
A signal frequency synthesizer for selectively providing an output signal at any one of a plurality of frequencies, comprising: a reference signal source, means for generating a plurality of binary related pulse trains which are in anti-coincidence and the frequencies of which have a predetermined fixed relationship with the frequency of said reference signal source, means for selectively adding together any desired combination of said binary related pulse trains, first and second frequency divider means for dividing the frequency of said added pulse trains, means responsive to the outputs of said divider means for alternately gating a number of pulses corresponding to the dividing factor of said divider means from the output of said means for generating binary-related pulse trains to the inputs of each of said divider means in turn, and first and second means responsive to the outputs of said first and second frequency divider means respectively for generating quadrature related square waves in accordance therewith.
Claim 3
Dependent Claim
26 words
The signal frequency synthesizer of claim 1 additionally including filter means for filtering the output of said square wave generating means to produce a sine wave.
Claim 4
Dependent Claim
197 words
In a signal frequency synthesizer, binary rate multiplier means for generating a pulse train which is a selected combination of binary related pulse trains, a reference frequency signal source for providing a reference signal to said binary rate multiplier means, the binary related pulse trains being fixedly related in frequency to that of said signal source, means for selecting a desired combination of said binary related pulse trains for the output of said binary rate multiplier means, first and second frequency dividers, means responsive to the outputs of said dividers for alternately gating a number of pulses corresponding to the dividing factor of said dividers from the output of said binary rate multiplier means to each of said dividers in turn, associated switching circuit means responsively connected to the output of each of said frequency dividers for generating a pair of quadrature related square wave output signals, and low pass filter means connected to each of said switching circuit means for converting said square waves to sine waves, whereby said sine waves have a frequency which is fixedly related to that of said reference frequency and in accordance with the selected combination of said binary related signals.
Claim 5
Dependent Claim
197 words
In a signal frequency synthesizer, binary rate multiplier means for generating a pulse train which is a selected combination of binary related pulse trains, a reference frequency signal source for providing a reference signal to said binary rate multiplier means, the binary related pulse trains being fixedly related in frequency to that of said signal source, means for selecting a desired combination of said binary related pulse trains for the output of said binary rate multiplier means, first and second frequency dividers, means responsive to the outputs of said dividers for alternately gating a number of pulses corresponding to the dividing factor of said dividers from the output of said binary rate multiplier means to each of said dividers in turn, associated switching circuit means responsively connected to the output of each of said frequency dividers for generating a pair of quadrature related square wave output signals, and low pass filter means connected to each of said switching circuit means for converting said square waves to sine waves, whereby said sine waves have a frequency which is fixedly related to that of said reference frequency and in accordance with the selected combination of said binary related signals.
Claim 6
Dependent Claim
66 words
The synthesizer of claim 3 wherein said gating means comprises an OR gate for receiving the outputs of said dividers, an AND gate interposed between the output of said binary rate multiplier means and each of said frequency dividers and switching means responsive to the output of said OR gate for alternately enabling each of said AND gates in accordance with successive outputs of said dividers.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-06-20 | 1975-12-20 | 1976-06-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-06-20 | 1979-12-20 | 1980-06-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-06-20 | 1983-12-20 | 1984-06-20 | $7700.00 | Window Closed / Lapsed |