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US3671820A Expired / Lapsed US ⏱️ 0.0 years remaining

High voltage thin-film transistor

Assignee: Individual
•
Filing: 1970-04-27
•
Granted: 1972-06-20
•
Expires: 1990-04-27
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Abstract

Abstract A high-voltage thin film field effect transistor has increased drain-source electrode separation and increased insulating layer thickness to avoid breakdown at high voltages. The insulating layer contains an electron-depleting film and an electronenhancing film so that the offset voltage may be kept sufficiently low. The surface of the semiconductor layer opposite that in contact with the insulating layer is contacted by an electron-depleting layer to avoid shunt current conduction via this surface.

Inventors

  • 👤 Rudolph R Haering
  • 👤 John F O'hanlon

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-25 15:43
CPC Classifications
H; H10; H10D; H10D99/00; H10D30/00; H10D30/60; H10D30/67

Claims Analysis

Total Claims: 15
Claim 1
Independent Claim 310 words
A high voltage thin film transistor of the insulated gate field effect type wherein the source-drain voltage is in excess of 200 volts, comprising: a semiconductor layer having first and second opposed major surfaces; a source electrode and a drain electrode at opposite ends of the semiconductor layer, the spacing between the source electrode and drain electrode being in excess of 0.01 cm; a composite insulating layer on said first major surface of the semiconductor layer and overlapping the area between the source and drain electrodes, the thickness of said layer being in excess of 8,000 A; a gate electrode on the surface of the composite insulating layer and overlapping the area between the source and drain electrodes and seperated from the semiconductor layer by the thickness of the insulating layer; and a depleting layer on the second surface of the semiconductor layer and overlapping the area between the source and drain electrodes, the thickness of said depleting layer being at least 1,000 A; the depleting layer effecting depletion of current carriers from the second surface of the semiconductor layer; the composite insulating layer comprising a film of depletion material and a film of enhancement material, said depletion material and said enhancement material of said composite layer together regulating the density of current carriers in said first surface of the semiconductor layer; whereby said depleting layer effects a first value of depletion of said second surface, and said composite insulating layer effects a second value of depletion of said first surface algebriacally less than said first value; said second value of depletion of said first surface being the algebraic sum of the depletion effected by said depletion material and of the enhancement effected by said enhancement material, with enhancement taken as a negative value of depletion; thereby controlling the values of the offset voltage and leakage current of said transistor.
Claim 2
Dependent Claim 310 words
A high voltage thin film transistor of the insulated gate field effect type wherein the source-drain voltage is in excess of 200 volts, comprising: a semiconductor layer having first and second opposed major surfaces; a source electrode and a drain electrode at opposite ends of the semiconductor layer, the spacing between the source electrode and drain electrode being in excess of 0.01 cm; a composite insulating layer on said first major surface of the semiconductor layer and overlapping the area between the source and drain electrodes, the thickness of said layer being in excess of 8,000 A; a gate electrode on the surface of the composite insulating layer and overlapping the area between the source and drain electrodes and seperated from the semiconductor layer by the thickness of the insulating layer; and a depleting layer on the second surface of the semiconductor layer and overlapping the area between the source and drain electrodes, the thickness of said depleting layer being at least 1,000 A; the depleting layer effecting depletion of current carriers from the second surface of the semiconductor layer; the composite insulating layer comprising a film of depletion material and a film of enhancement material, said depletion material and said enhancement material of said composite layer together regulating the density of current carriers in said first surface of the semiconductor layer; whereby said depleting layer effects a first value of depletion of said second surface, and said composite insulating layer effects a second value of depletion of said first surface algebriacally less than said first value; said second value of depletion of said first surface being the algebraic sum of the depletion effected by said depletion material and of the enhancement effected by said enhancement material, with enhancement taken as a negative value of depletion; thereby controlling the values of the offset voltage and leakage current of said transistor.
Claim 3
Dependent Claim 50 words
A transistor as defined in claim 1, wherein the film of depletion material is in contact with the semiconductor layer and the film of enhancement material is in contact with the film of depletion material and separated from the semiconductor layer by the thickness of the film of depletion material.
Claim 4
Dependent Claim 37 words
A transistor as defined in claim 2, wherein the thickness of the composite insulating layer and the separation between the source and drain electrodes are sufficiently large to avoid breakdown of the transistor under preselected voltage conditions.
Claim 5
Dependent Claim 60 words
A transistor as defined in claim 3 wherein the characteristics and thickness of the film of depletion material and of the film of enhancement material are selected so that the bulk potential of the semiconductor layer is equal to the surface potential of the semiconductor layer at that surface of the semiconductor layer in contact with the composite insulating layer.
Claim 6
Dependent Claim 28 words
A transistor as defined in claim 3 wherein the semiconductor layer is cadmium sulfide, the said depletion materials are calcium fluoride, and the enhancement material is silicon monoxide.
Claim 7
Dependent Claim 28 words
A transistor as defined in claim 5 wherein the composite insulating layer additionally includes a film of insulating material between the silicon monoxide film and the gate electrode.
Claim 8
Dependent Claim 17 words
A transistor as defined in claim 6 wherein the additional film of insulating material is germanium oxide.
Claim 9
Dependent Claim 28 words
A transistor as defined in claim 3 wherein the semiconductor layer is cadmium selenide, the said depletion materials are calcium fluoride, and the enhancement material is silicon monoxide.
Claim 10
Dependent Claim 28 words
A transistor as defined in claim 8 wherein the composite insulating layer additionally includes a film of insulating material between the silicon monoxide film and the gate electrode.
Claim 11
Dependent Claim 17 words
A transistor as defined in claim 9 wherein the additional film of insulating material is geRmanium oxide.
Claim 12
Dependent Claim 47 words
A transistor as defined in claim 10 wherein the semiconductor layer is of the order of 1,500 A thick, the calcium fluoride film in the composite insulating layer is of the order of 150 A thick and the silicon monoxide film is at least 2,000 A thick.
Claim 13
Dependent Claim 45 words
A transistor as defined in claim 11 wherein the depleting layer is at least 2,000 A thick, the composite insulating layer is of the order of 10,000 A thick, and the separation between the source and drain electrodes is of the order of 0.025 cm.
Claim 14
Dependent Claim 47 words
A transistor as defined in claim 7 wherein the semiconductor layer is of the order of 1,500 A thick, the calcium fluoride film in the composite insulating layer is of the order of 150 A thick and the silicon monoxide film is at least 2,000 A thick.
Claim 15
Dependent Claim 45 words
A transistor as defined in claim 13 wherein the depleting layer is at least 2,000 A thick, the composite insulating layer is of the order of 10,000 A thick, and the separation between the source and drain electrodes is of the order of 0.025 cm.

References Cited (Backward Citations)

US3385731A Cited
US3307089A Cited
US3502950A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1975-06-20 1975-12-20 1976-06-20 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1979-06-20 1979-12-20 1980-06-20 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1983-06-20 1983-12-20 1984-06-20 $7700.00 Window Closed / Lapsed

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