Sampling decoder for delay modulation signals

Claim 2

A decoder for an information signal in which a transition occurs at the center of a bit cell containing a ''''1'''' and a transition occurs at the boundary between two successive bit cells containing ''''0s,'''' comprising means to compare the polarities of the information signal just prior to and just following the center of a bit cell and generate a first decoded signal when the polarities are different, means to compare the polarities of the information signal at the beginning and end of a bit cell and generate a second decoded signal when the polarities are different, and means to ''''and'''' said first and second decoded signals to produce an NRZ output signal.

Claim 3

A decoder for an input information signal in which a transition occurs at the center of a bit cell containing a ''''1'''' and a transition occurs at the boundary between two successive bit cells containing ''''0s,'''' comprising a limiter, means to a-c couple the input information signal to said limiter to produce a binary information signal having a given binary value when the input signal has a given polarity relative to zero volts, means to compare the binary value of the binary information signal just prior to the center of a bit cell with the binary value of the signal just following the center of the bit cell, and generate a first decoded signal when the values are different, means to compare the binary value of the binary information signal at the beginning of a bit cell with the binary value of the signal at the end of the bit cell, and generate a second decoded signal when the values are different, and means to ''''and'''' said first and second decoded signals to produce an NRZ output signal.

Claim 4

A decoder for an input information signal in which a transition occurs at the center of a bit cell containing a ''''1'''' and a transition occurs at the boundary between two successive bit cells containing ''''0s,'''' comprising a limiter, means to a-c couple the input information signal to said limiter to produce a binary information signal having a given binary value when the input signal has a given polarity relative to zero volts, means to compare the binary value of the binary information signal just prior to the center of a bit cell with the binary value of the signal just following the center of the bit cell, and generate a first decoded signal when the values are different, means to compare the binary value of the binary information signal at the beginning of a bit cell with the binary value of the signal at the end of the bit cell, and generate a second decoded signal when the values are different, and means to ''''and'''' said first and second decoded signals to produce an NRZ output signal.

Claim 5

A decoder according to claim 2 in which the comparisons made just prior to and just following the center of a bit cell are made at a quarter of a bit cell prior to and a quarter of a bit cell following the center of bit cell.

Claim 6

A decoder for an input information signal in which a transition occurs at the center of a bit cell containing a ''''1'''' and a transition occurs at the boundary between two successive bit cells containing ''''0s,'''' comprising a first limiter, means to a-c couple the input information signal with high frequency emphasis to said first limiter to produce a first binary information signal having a given binary value when the input signal has a given polarity relative to zero volts, a second limiter, means to a-c couple the information signal without high frequency emphasis to said second limiter to produce a second binary information signal having a given binary value when the input signal has a given polarity relative to zero volts, means to compare the binary value of the first binary information signal a quarter of a bit cell prior to the center of the bit cell with the binary value of the signal a quarter of a bit cell following the center of the bit cell, and generate a first decoded signal when the values are different, means to compare the binary value of the second binary information signal at the beginning of a bIt cell with the binary value of the signal at the end of a bit cell, and generate a second decoded signal when the values are different, and means to ''''and'''' said first and said second decoded signals to produce an NRZ output signal.

Claim 7

A decoder for an input information signal in which a transition occurs at the center of a bit cell containing a ''''1'''' and a transition occurs at the boundary between two successive bit cells containing ''''0s,'''' comprising a first limiter, means to a-c couple the input information signal with high frequency emphasis to said first limiter to produce a first binary information signal having a given binary value when the input signal has a given polarity relative to zero volts, a second limiter, means to a-c couple the information signal without high frequency emphasis to said second limiter to produce a second binary information signal having a given binary value when the input signal has a given polarity relative to zero volts, means to compare the binary value of the first binary information signal a quarter of a bit cell prior to the center of the bit cell with the binary value of the signal a quarter of a bit cell following the center of the bit cell, and generate a first decoded signal when the values are different, means to compare the binary value of the second binary information signal at the beginning of a bIt cell with the binary value of the signal at the end of a bit cell, and generate a second decoded signal when the values are different, and means to ''''and'''' said first and said second decoded signals to produce an NRZ output signal.