← Back to Patent Explorer
US3670185A Expired / Lapsed US ⏱️ 0.0 years remaining

Industrial technique

Assignee: Schlumberger Technology Corp
•
Filing: 1970-04-15
•
Granted: 1972-06-13
•
Expires: 1990-04-15
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract An illustrative embodiment of the invention relates to a circuit for a nuclear magnetic logging tool in which two sets of two parallel connected field effect transistors (FET), are coupled to respective gate voltages that are of equal magnitude and of opposite polarity. During polarization, the FETs are in a low impedance condition to avoid being subjected to large voltages. The method of biasing, together with the parallel connection of the FETs ensures symmetrical voltages with respect to ground across the coil. At the end of polarizing, the coil voltage reverses causing conduction to occur in a Zener diode which is connected across the coil. When the reverse voltage of the coil drops below a predetermined level, the Zener diode stops conducting and the circuit rings at its resonant frequency for a few milliseconds. To further reduce the charge in the circuit, a low value critical damping resistance is applied across the coil through another field effect transistor. After most of the stored charge has been dissipated, both FET sets are switched to a high impedance state in order to apply the formation fluid nuclear magnetic resonance signal to the downhole amplification system input.

Inventors

  • 👤 Clifford Vermette

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-25 21:19
CPC Classifications
G; G01; G01V; G01V3/00; G01V3/18; G01V3/32; H; H03; H03K; H03K17/00; H03K17/51; H03K17/56; H03K17/687; H03K17/6871; H03K3/00; H03K3/80

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 128 words
In a circuit having an inductor and means coupled to the inductor for changing the magnitude of the impedence across the terminals of the inductor, the combination of, two sets of field-effect transistors, each set having at least two field-effect transistors therein, the field-effect transistors in each set having first and second electrodes and a gate electrode, the first, second and gate electrode of each field-effect transistor in each set of field-effect transistors being coupled respectively to the first, second and gate electrode of the other field-effect transistors in the set, the second electrodes of one set of field-effect transistors being coupled to the second electrodes of the other set, and the first electrodes of each set of field-effect transistors being coupled to opposite terminals of said inductor.
Claim 2
Dependent Claim 128 words
In a circuit having an inductor and means coupled to the inductor for changing the magnitude of the impedence across the terminals of the inductor, the combination of, two sets of field-effect transistors, each set having at least two field-effect transistors therein, the field-effect transistors in each set having first and second electrodes and a gate electrode, the first, second and gate electrode of each field-effect transistor in each set of field-effect transistors being coupled respectively to the first, second and gate electrode of the other field-effect transistors in the set, the second electrodes of one set of field-effect transistors being coupled to the second electrodes of the other set, and the first electrodes of each set of field-effect transistors being coupled to opposite terminals of said inductor.
Claim 3
Dependent Claim 27 words
The circuit of claim 1 wherein the first electrodes of each set of field-effect transistors are the drain electrodes and the second electrodes are the source electrodes.
Claim 4
Dependent Claim 87 words
The circuit of claim 2 wherein the gate electrodes of one of the sets of the field-effect transistors are coupled to a first voltage source having a first polarity and the gate electrodes of the other set of the field-effect transistors are coupled to a second voltage source having a magnitude equal to that of the first voltage source and having a polarity opposite to that of the first voltage source during the time that the two sets of the field-effect transistors are in the ON condition.

References Cited (Backward Citations)

US3077545A Cited
US3252011A Cited
US3521242A Cited
US3539823A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1975-06-13 1975-12-13 1976-06-13 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1979-06-13 1979-12-13 1980-06-13 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1983-06-13 1983-12-13 1984-06-13 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag