Memory cells

Claim 2

A memory cell comprising a bistable circuit, first, second and third signal access paths, two selectably low impedance paths, and two further selectably low impedance paths; one of said selectably low impedance paths being connected between said first and said third signal access paths and the other being connected between said second and said third signal access paths, one state of the bistable circuit setting one of said selectably low impedance paths to be of low impedance and the other to be of high impedance and the other state of the bistable circuit setting the other of said selectably low impedance paths to be of low impedance and the one to be of high impedance; said bistable circuit comprising two cross-coupled active elements, one of said two further selectably low impedance paths being connected across each active element, the bistable circuit being set to one state to store a ''''1'''' by selection of one of said two further selectably low impedance paths to be of low impedance in dependence on the state of said first and said third signal access paths and to the other state to store a ''''0'''' by selection of the other of said two further selectably low impedance paths to be of low impedance in dependence on the state of said second and said third signal access paths.

Claim 3

A memory cell as claimed in claim 1 and wherein said bistable circuit comprises two p-type M.O.S. transistors, the gate electrode of one being connected to the drain electrode of the other, and the gate electrode of the other being connected to the drain electrode of the one, one of said two further selectably low impedance paths being connected between the drain and source electrodes of each transistor.

Claim 4

A memory cell as claimed in claim 1 and wherein said first mentioned two selectably low impedance paths each comprises a M.O.S. transistor, one having its drain electrode connected to said first signal access path, its source electrode connected to said third signal access path and its gate electrode connected to one of the active elements in the bistable circuit and the other having its drain electrode connected to said second signal access path, its source connected to said third signal access path and its gate electrode connected to the other of the active elements in the bistable circuit.

Claim 5

A memory cell as claimed in claim 3 and wherein the active elements forming the bistable circuit are M.O.S. transistors and the gate electrodes of the M.O.S. transistors forming said first mentioned two selectably low impedance paths are connected to the appropriate drain electrodes of the M.O.S. transistors forming the bistable circuit.

Claim 6

A memory cell as claimed in claim 1 and wherein said two further selectably low impedance paths each comprises two M.O.S. transistors conNected with their source/drain paths in series across one of the active elements forming the bistable circuit, one of the serially connected two transistors having its gate electrode connected to the third signal access path and the other having its gate electrode connected to an appropriate one of the first and second signal access paths.

Claim 7

An associative memory store comprising an array of memory cells as claimed in claim 5 connected with common first, second, and third signal access paths.

Claim 8

A memory cell comprising, in combination: a bistable circuit comprising a pair of cross-coupled active elements having two output terminals, one for each stable state; first, second and third signal access path means for writing in and reading out with respect to said bistable circuit; first impedance means connected across one of said active elements for producing one stable state output at one of said output terminals, said first impedance means being connected to said first and said second signal access path means for producing such one stable state output in response to write-in signals applied simultaneously at said first and said second signal access path means; second impedance means connected across the other of said active elements for producing the other stable state output at the other of said output terminals, said second impedance means being connected to said second and said third signal access path means for producing such other stable state output in response to write-in signals applied simultaneously at said second and third signal access path means; third impedance means for providing a low impedance path between said first and said second signal access path means in response to the presence of said other stable state output, and fourth impedance means for providing a low impedance path between said third and said second signal access path means in response to the presence of said one stable state output.

Claim 9

A memory cell comprising, in combination: a bistable circuit comprising a pair of cross-coupled active elements having two output terminals, one for each stable state; first, second and third signal access path means for writing in and reading out with respect to said bistable circuit; first impedance means connected across one of said active elements for producing one stable state output at one of said output terminals, said first impedance means being connected to said first and said second signal access path means for producing such one stable state output in response to write-in signals applied simultaneously at said first and said second signal access path means; second impedance means connected across the other of said active elements for producing the other stable state output at the other of said output terminals, said second impedance means being connected to said second and said third signal access path means for producing such other stable state output in response to write-in signals applied simultaneously at said second and third signal access path means; third impedance means for providing a low impedance path between said first and said second signal access path means in response to the presence of said other stable state output, and fourth impedance means for providing a low impedance path between said third and said second signal access path means in response to the presence of said one stable state output.

Claim 10

A memory cell comprising, in combination: a bistable circuit having two stable state outputs; first, second and third signal access path means for controlling said bistable circuit to effect storage therein and for determining the storage condition of said bistable circuit without altering its stable state; first means connected to aid first and second signal access path means for effecting one stable state of said bistable circuit in response to write-in signals applied simultaneously to said first and said second signal access path means and for effecting a low impedance path between said first and said second signal access path means only in response to attainment of said one stable state; and second means connected to said second and said third signal access path means for effecting the other stable state of said bistable circuit in response to write-in signals applied simultaneously to said second and said third signal access path means and for effecting a low impedance path between said second and said third signal access path means only in response to attainment of said other stable state.

Claim 11

A memory cell comprising, in combination: a bistable circuit having two stable state outputs; first, second and third signal access path means for controlling said bistable circuit to effect storage therein and for determining the storage condition of said bistable circuit without altering its stable state; first means connected to aid first and second signal access path means for effecting one stable state of said bistable circuit in response to write-in signals applied simultaneously to said first and said second signal access path means and for effecting a low impedance path between said first and said second signal access path means only in response to attainment of said one stable state; and second means connected to said second and said third signal access path means for effecting the other stable state of said bistable circuit in response to write-in signals applied simultaneously to said second and said third signal access path means and for effecting a low impedance path between said second and said third signal access path means only in response to attainment of said other stable state.

Claim 12

A memory cell as defined in claim 7 wherein said first impedance means comprises a pair of transistors having controllable current conducting paths connected in series and having control electrodes connected respectively to said first and said second signal access path means, said second impedance means comprises a pair of transistors having controllable current conducting paths connected in series and having control electrodes connected respectively to said second and said third signal access path means, said third impedance means comprises a transistor having a controllable current conducting path connecting said first and said second signal access path means and having a control electrode connected to said other output terminal, and said fourth impedance means comprises a transistor having a controllable current conducting path connecting said second and said third signal access path means and having a control eleCtrode connected to said one output terminal.

Claim 13

A memory cell as defined in claim 8 wherein said first means includes a pair of transistors having series connected controllable current paths for affecting the output state of said bistable circuit and control electrodes connected respectively to said first and said second signal access path means, and said second means includes a pair of transistors having series connected controllable current paths for affecting the output state of said bistable circuit and control electrodes connected respectively to said second and said third signal access path means.

Claim 14

A memory cell as defined in claim 10 wherein said first means also includes a further transistor having a controllable current conducting path connecting said first and said second signal access path means and a control electrode connected to said bistable circuit for current control in response to one output state thereof, and said second means also includes a further transistor having a controllable current conducting path connecting said second and said third signal access path means and a control electrode connected to said bistable circuit for current control in response to the other output state thereof.

Claim 15

A memory cell as defined in claim 8 wherein said first means includes a further transistor having a controllable current conducting path connecting said first and said second signal access path means and a control electrode connected to said bistable circuit for current control in response to one output state thereof, and said second means includes a further transistor having a controllable current conducting path connecting said second and said third signal access path means and a control electrode connected to said bistable circuit for current control in response to the other output state thereof.