Programable asynchronous data buffer having means to transmit error protected channel control signals

Claim 2

An asynchronous data buffer comprising a. an input register for receiving and storing a start-stop primary data character having from 1 to N bits; b. input means for receiving a secondary control data character having from 1 to N bits; c. an output transfer register coupled to said input register and said secondary control data receiving means for storing either of said primary or secondary data characters; d. first circuit means for generating an output signal when said output register is empty; e. second circuit means responsive to said input register for generating an input full signal when said input register is full; f. first gate means coupled to said input register full signal generating means and to said output register empty signal generating means for transferring primary data from said input register to said output register when said input full and output empty signals are generated; g. means for receiving an input high speed burst timing signal; h. circuit means responsive to said burst timing signal receiving means and said output register empty signal generating means for transferring a secondary data character from said character receiving means into the output register when said input register is empty; and i. circuit means responsive to said high speed burst timing signal receiving means for shifting data in the output register to an output line.

Claim 3

Apparatus in accordance with claim 1 wherein a first identifying indicator bit is transmitted with said primary data and a second identifying indicator bit is transmitted with said secondary control data.

Claim 4

An asynchronous data buffer for receiving channel data including intermixed characters of primary data identified with a first indicator bit and secondary data characters identified with a second indicator bit, said apparatus comprising: a. an input register for sequentially receiving and storing incoming primary and secondary data characters; b. an output register for storing primary data characters to be delivered to a start-stop data receiving terminal; c. a secondary register for storing secondary data characters to be delivered to a supervisory and control test terminal; d. first circuit means associated with said input register for developing a primary data input to output register transfer control signal in response to a stored identifying first indicator bit; e. second circuit means associated with said input register for identifying a secondary data indicator bit and producing a secondary data input to secondary data output register transfer control signal, f. means responsive to said first circuit means for transferring said primary data from said input register to said output register upon the occurrence of said primary data input to output register transfer signal, and g. means responsive to said second circuit means for transferring said secondary data from said secondary register to said output register upon the occurrence of said secondary data input to secondary data output register transfer control signal.

Claim 5

An asynchronous data buffer for receiving channel data including intermixed characters of primary data identified with a first indicator bit and secondary data characters identified with a second indicator bit, said apparatus comprising: a. an input register for sequentially receiving and storing incoming primary and secondary data characters; b. an output register for storing primary data characters to be delivered to a start-stop data receiving terminal; c. a secondary register for storing secondary data characters to be delivered to a supervisory and control test terminal; d. first circuit means associated with said input register for developing a primary data input to output register transfer control signal in response to a stored identifying first indicator bit; e. second circuit means associated with said input register for identifying a secondary data indicator bit and producing a secondary data input to secondary data output register transfer control signal, f. means responsive to said first circuit means for transferring said primary data from said input register to said output register upon the occurrence of said primary data input to output register transfer signal, and g. means responsive to said second circuit means for transferring said secondary data from said secondary register to said output register upon the occurrence of said secondary data input to secondary data output register transfer control signal.

Claim 6

An asynchronous data buffer in accordance with claim 3 further comprising, means for supplying the data characters stored in said secondary register to a digital filter, the output of which supplies error protected control signals to a supervisory and control test terminal.

Claim 7

In an asynchronous data buffer for receiving channel data including intermixed characters of primary data and secondary data characters having at least one fixed filler bit, plural coded control bits and an identifying indicator bit, digital filter means for protecting against erroneous identification of said secondary data characters comprising: a. first circuit means responsive to said indicator bit for producing a first validation control signal; b. second digital comparator means for comparing the fixed filler bit of a secondary character with a fixed digital reference and producing on condition of identity a second validation control signal; c. third digital comparator means for comparing the said plural coded control bits of successive transmissions of a secondary data character and producing on condition of identity a third validation control signal; and d. circuit means responsive to said first circuit means and said second and third comparators for transferring the received secondary data characters to an error protected output terminal upon the occurrence of said first, second and third validation control signals.

Claim 8

In an asynchronous data buffer for receiving channel data including intermixed characters of primary data and secondary data characters having at least one fixed filler bit, plural coded control bits and an identifying indicator bit, digital filter means for protecting against erroneous identification of said secondary data characters comprising: a. first circuit means responsive to said indicator bit for producing a first validation control signal; b. second digital comparator means for comparing the fixed filler bit of a secondary character with a fixed digital reference and producing on condition of identity a second validation control signal; c. third digital comparator means for comparing the said plural coded control bits of successive transmissions of a secondary data character and producing on condition of identity a third validation control signal; and d. circuit means responsive to said first circuit means and said second and third comparators for transferring the received secondary data characters to an error protected output terminal upon the occurrence of said first, second and third validation control signals.

Claim 9

In the operation of an asynchronous data buffer for receiving channel data including secondary control data characters having at least one fixed filler bit, plural coded control bits and an identifying indicator bit, a method for protecting against erroneous identification of said secondary characters comprising the steps of: a. testing a received character for the presence of an identifying indicator bit to develop a first validation control signal; b. comparing the fixed portion of said character with a programmed reference to produce on condition of identity a second validation control signal; c. comparing the plural coded control bits of a first received character with those in a second received character to produce on condition of identity a third validation control signal; and d. producing a character validation signal in response to the coincidence of said first, second and third validation control signals.

Claim 10

In the operation of an asynchronous data buffer for receiving channel data including secondary control data characters having at least one fixed filler bit, plural coded control bits and an identifying indicator bit, a method for protecting against erroneous identification of said secondary characters comprising the steps of: a. testing a received character for the presence of an identifying indicator bit to develop a first validation control signal; b. comparing the fixed portion of said character with a programmed reference to produce on condition of identity a second validation control signal; c. comparing the plural coded control bits of a first received character with those in a second received character to produce on condition of identity a third validation control signal; and d. producing a character validation signal in response to the coincidence of said first, second and third validation control signals.

Claim 11

In the operation of an asynchronous data buffer for receiving channel data including secondary control data characters having an identifying indicator bit and plural coded control bits, a method for protecting against erroneous identification of said secondary characters comprising the steps of: a. testing a received character for the presence of an identifying indicator bit to develop a first validation control signal; b. comparing the plural coded control bits of a first received character with those in a second received character to produce on condition of identity a second validation control signal; and c. producing a character validation signal in response to the coincidence of said first and second control signals.

Claim 12

In the operation of an asynchronous data buffer for receiving channel data including secondary control data characters having an identifying indicator bit and plural coded control bits, a method for protecting against erroneous identification of said secondary characters comprising the steps of: a. testing a received character for the presence of an identifying indicator bit to develop a first validation control signal; b. comparing the plural coded control bits of a first received character with those in a second received character to produce on condition of identity a second validation control signal; and c. producing a character validation signal in response to the coincidence of said first and second control signals.