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US3668560A
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US
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Pulse-width frequency modulation device
Assignee: Research Corp
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Filing: 1970-07-09
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Granted: 1972-06-06
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Expires: 1990-07-09
Abstract
Abstract As described herein, a train of pulses used to control a servomotor is modulated in accordance with the values of a varying digital input signal. To obtain accuracy of control, the digital input signal is divided into two components; a first group of bits representing integer order values; and a second group of bits representing fractional order data. A modulating circuit responds to the integer order bits to width modulate the pulse train in accordance with the magnitude represented by the integer order bits. The fractional order data bits are accumulated until the sum thereof at least equals the value of the least significant bit of the integer order component. At this time, the sum signal is added to the integer order data to add an increment of width modulation to the pulse then being modulated.
Inventors
- 👤 Joseph J Padalino
- 👤 Alfons A Tuszynski
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 16:32
CPC Classifications
G; G05; G05B; G05B11/00; G05B11/01; G05B11/26; G05B11/28; H; H03; H03M; H03M1/00; H03M1/66; H03M1/82; H03M1/822
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
84 words
In a pulse-width frequency modulating system for modulating a train of pulses in accordance with the values of first and second digital input signals, the improvement comprising modulating circuit means, said modulating circuit means comprising first circuit means for width modulating the pulses of the pulse train in accordance with the magnitudinal information of the first signal and second circuit means for further modulating the widths of certain pulses in the pulse train in accordance with the magnitudinal information of the second input signal.
Claim 2
Dependent Claim
84 words
In a pulse-width frequency modulating system for modulating a train of pulses in accordance with the values of first and second digital input signals, the improvement comprising modulating circuit means, said modulating circuit means comprising first circuit means for width modulating the pulses of the pulse train in accordance with the magnitudinal information of the first signal and second circuit means for further modulating the widths of certain pulses in the pulse train in accordance with the magnitudinal information of the second input signal.
Claim 3
Dependent Claim
91 words
A pulse-width frequency modulating system according to claim 1 wherein the first digital input signal includes a first group of bits representative of integer order data and the second digital input signal includes a second group of bits representative of fractional order data and wherein the first circuit means width modulates the pulse train in accordance with the magnitude represented by integer order bits and the second circuit means modulates the widths of certain pulses in the pulse train at a frequency determined by the magnitude of the fractional order bits.
Claim 4
Dependent Claim
71 words
A pulse-width frequency modulating system as defined in claim 2 wherein the second circuit means comprises means for accumulating the fractional order bits until the accumulation equals at least the value of the least significant bit of the integer order data and adder means for adding the accumulation of the integer order data to add an increment of width modulation to the pulse then being modulated by the first circuit means.
Claim 5
Dependent Claim
86 words
A pulse-width frequency modulating system according to claim 3 wherein each digital input signal includes a sign bit, an integer order component weighted in positive powers of 2 and a fractional order component weighted in negative powers of 2 and wherein the first circuit means comprises format converter means having a first means for detecting the presence of a negative sign bit and a second means responsive to the detection of a negative sign bit for producing a one''s complement conversion of each integer order bit.
Claim 6
Dependent Claim
47 words
A pulse-width frequency modulating system according to claim 3 further comprising detector means for detecting the presence of the first group of integer order bits representative of a maximum value for disabling the adding means to preclude the addition of the accumulatIon to the integer order data.
Claim 7
Dependent Claim
65 words
A pulse-width frequency modulating system according to claim 3 wherein the first circuit means further includes width modulating circuit means responsive to the addition of the accumulation and the integer order data and responsive to the pulse train for producing a corresponding train of pulses wherein the widths of the individual pulses are proportional to the addition of the accumulation and the integer order data.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-06-06 | 1975-12-06 | 1976-06-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-06-06 | 1979-12-06 | 1980-06-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-06-06 | 1983-12-06 | 1984-06-06 | $7700.00 | Window Closed / Lapsed |