Patent US4274673A successfully refreshed from Google Patents.
Patent US3668438A successfully refreshed from Google Patents.
US3668438A
Expired / Lapsed
US
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Shift register stage using insulated-gate field-effect transistors
Assignee: AT&T Inc
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Filing: 1970-07-09
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Granted: 1972-06-06
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Expires: 1990-07-09
Abstract
Abstract An insulated-gate field-effect transistor (IGFET) shift register stage occupies less semiconductor chip area because a separate ground lead to the gate and drain electrodes of a pair of IGFET load devices is eliminated. This lead is eliminated by substituting therefor a connection from those devices to a first clock phase which controls conduction through that pair of load devices and through a pair of cross-coupling transistors. A second clock phase, which is out of phase with the first clock phase, controls conduction through both an input transistor of the stage and a third IGFET load device connected to an output terminal of the stage.
Inventors
- 👤 Ernam Fillmore King
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 07:50
CPC Classifications
G; G11; G11C; G11C19/00; G11C19/28
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
96 words
A shift register stage comprising a pair of insulated-gate field-effect transistors, a pair of devices cross-coupling the pair of transistors, a pair of load devices, each connected to a different one of the transistors, means for controlling coincidental conduction through the pair of cross-coupling devices and through the pair of load devices, an input device, a third load device connected to one of the transistors, and means for controlling coincidental conduction through the input device and the third load device alternatively with respect to the conduction through the cross-coupling devices and the pair of load devices.
Claim 2
Dependent Claim
96 words
A shift register stage comprising a pair of insulated-gate field-effect transistors, a pair of devices cross-coupling the pair of transistors, a pair of load devices, each connected to a different one of the transistors, means for controlling coincidental conduction through the pair of cross-coupling devices and through the pair of load devices, an input device, a third load device connected to one of the transistors, and means for controlling coincidental conduction through the input device and the third load device alternatively with respect to the conduction through the cross-coupling devices and the pair of load devices.
Claim 3
Dependent Claim
243 words
A circuit comprising first, second, third, fourth, fifth, sixth, seventh, and eighth semiconductor devices, each having source, gate, and drain electrodes, a source of reference potential, means connecting the source electrodes of the first and second devices to the reference potential source, means connecting the drain electrode of the first device to the source electrode of the third device, means connecting the drain electrode of the third device to the gate electrode of the second device, means connecting the drain electrode of the second device to the source electrode of the fourth device, means connecting the drain electrode of the fourth device to the gate electrode of the first device, means connecting the source electrode of the fifth device to the drain electrode of the first device, means connecting the source electrode of the sixth device to the drain electrode of the second device, first and second clock-drive phases substantially out-of-phase with each other, means connecting the first clock-drive phase to the gate electrodes of the third and fourth devices and to the gate and drain electrodes of the fifth and sixth devices, means connecting the drain electrode of the seventh device to the gate electrode of the first device, means connecting the source electrode of the eighth device to the drain electrode of the second device, and means connecting the second clock-drive phase to the gate electrode of the seventh device and to the gate and drain electrodes of the eighth device.
Claim 4
Dependent Claim
243 words
A circuit comprising first, second, third, fourth, fifth, sixth, seventh, and eighth semiconductor devices, each having source, gate, and drain electrodes, a source of reference potential, means connecting the source electrodes of the first and second devices to the reference potential source, means connecting the drain electrode of the first device to the source electrode of the third device, means connecting the drain electrode of the third device to the gate electrode of the second device, means connecting the drain electrode of the second device to the source electrode of the fourth device, means connecting the drain electrode of the fourth device to the gate electrode of the first device, means connecting the source electrode of the fifth device to the drain electrode of the first device, means connecting the source electrode of the sixth device to the drain electrode of the second device, first and second clock-drive phases substantially out-of-phase with each other, means connecting the first clock-drive phase to the gate electrodes of the third and fourth devices and to the gate and drain electrodes of the fifth and sixth devices, means connecting the drain electrode of the seventh device to the gate electrode of the first device, means connecting the source electrode of the eighth device to the drain electrode of the second device, and means connecting the second clock-drive phase to the gate electrode of the seventh device and to the gate and drain electrodes of the eighth device.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-06-06 | 1975-12-06 | 1976-06-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-06-06 | 1979-12-06 | 1980-06-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-06-06 | 1983-12-06 | 1984-06-06 | $7700.00 | Window Closed / Lapsed |