Patent US3668436A successfully refreshed from Google Patents.
US3668436A
Expired / Lapsed
US
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Circuit apparatus for supplying first and second trains of mutually exclusive clock pulses
Assignee: Monroe Systems for Business Inc
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Filing: 1969-12-15
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Granted: 1972-06-06
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Expires: 1989-12-15
Abstract
Abstract A two phase clock circuit particularly useful for driving logic circuitry whose operation requires the definition of two substantially non-overlapping clock phases. The clock circuit includes a square wave oscillator having true and complementary output terminals, each driving a different power amplifier. Each oscillator output terminal is connected to its associated power amplifier through a NOR gate. The second terminal of each NOR gate is connected to the output of the opposite power amplifier so that neither power amplifier can begin to form a clock pulse until the clock pulse formed by the other power amplifier has terminated, or in other words, until the output voltage of the other power amplifier has fallen to a defined threshold level.
Inventors
- 👤 Stanley H Bacon
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 08:28
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/26; H03K3/28; H03K3/281; H03K3/282; H03K3/2821; H03K5/00; H03K5/15; H03K5/151; H03K5/1515
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
240 words
Circuit apparatus for supplying first and second trains of complementary clock pulses, said apparatus comprising: an oscillator circuit having first and second output terminals and including means for alternately providing first polarity signal transitions on said first and second output terminals; first and second power amplifiers, each having an input terminal and an output terminal and including means providing an output signal at said output terminal at an active level in response to a first polarity signal transition applied to the input terminal thereof; a first means coupling said oscillator circuit first output terminal to said first power amplifier input terminal, said first means including a first threshold gate means for maintaining said first power amplifier output signal at said active level subsequent to the termination of a first polarity signal transition on said oscillator circuit first output terminal; a second means coupling said oscillator circuit second output terminal to said second power amplifier input terminal, said second means including second threshold gate means for maintaining said second power amplifier output signal at said active level subsequent to the termination of a first polarity signal transition on said oscillator circuit second output terminal; first disabling means responsive to said second power amplifier output signal being at said active level for disabling said first threshold gate means; and second disabling means responsive to said first power amplifier output signal being at said active level for disabling said second threshold gate means.
Claim 2
Dependent Claim
240 words
Circuit apparatus for supplying first and second trains of complementary clock pulses, said apparatus comprising: an oscillator circuit having first and second output terminals and including means for alternately providing first polarity signal transitions on said first and second output terminals; first and second power amplifiers, each having an input terminal and an output terminal and including means providing an output signal at said output terminal at an active level in response to a first polarity signal transition applied to the input terminal thereof; a first means coupling said oscillator circuit first output terminal to said first power amplifier input terminal, said first means including a first threshold gate means for maintaining said first power amplifier output signal at said active level subsequent to the termination of a first polarity signal transition on said oscillator circuit first output terminal; a second means coupling said oscillator circuit second output terminal to said second power amplifier input terminal, said second means including second threshold gate means for maintaining said second power amplifier output signal at said active level subsequent to the termination of a first polarity signal transition on said oscillator circuit second output terminal; first disabling means responsive to said second power amplifier output signal being at said active level for disabling said first threshold gate means; and second disabling means responsive to said first power amplifier output signal being at said active level for disabling said second threshold gate means.
Claim 3
Dependent Claim
69 words
The circuit apparatus of claim 1 wherein said first threshold gate means includes a first zener diode connected in series with a first resistor between said first power amplifier input terminal and a source of reference potential; and wherein said second threshold gate means includes a second zener diode connected in series with a second resistor between said second poweR amplifier input terminal and said source of reference potential.
Claim 4
Dependent Claim
65 words
The circuit apparatus of claim 2 wherein said first disabling means includes a first diode connected between said second power amplifier output terminal and the junction between said first zener diode and said first resistor; and wherein said second disabling means includes a second diode connected between said first power amplifier output terminal and the junction between said second zener diode and said second resistor.
Claim 5
Dependent Claim
284 words
Circuit apparatus for supplying first and second trains of complementary clock pulses, said apparatus comprising: an oscillator including first and second transistors, each having an output electrode; a first resistor having a first end connected to said first transistor output electrode and a second end adapted to be connected to a source of relatively positive potential; a second resistor having a first end connected to said second transistor output electrode and a second end adapted to be connected to said source of relatively positive potential; a first power amplifier having an output terminal and including an input transistor having a control electrode and input and output current electrodes; a second power amplifier having an output terminal and including an input transistor having a control electrode and input and output current electrodes; means connecting a source of potential across said input and output current electrodes of said first and second power amplifier input transistors; means connecting said first transistor output electrode to said first power amplifier input transistor control electrodes; means connecting said second transistor output electrode to said second power amplifier input transistor control electrode; a first zener diode and a third resistor connected in series between said first power amplifier input transistor control electrode and said source of relatively negative potential; a second zener diode and a fourth resistor connected in series between said second power amplifier input transistor control electrode and said source of relatively negative potential; first diode means connecting said second power amplifier output terminal to the junction between said first zener diode and said third resistor; and second diode means connecting said first power amplifier output terminal to the junction between said second zener diode and said fourth resistor.
Claim 6
Dependent Claim
284 words
Circuit apparatus for supplying first and second trains of complementary clock pulses, said apparatus comprising: an oscillator including first and second transistors, each having an output electrode; a first resistor having a first end connected to said first transistor output electrode and a second end adapted to be connected to a source of relatively positive potential; a second resistor having a first end connected to said second transistor output electrode and a second end adapted to be connected to said source of relatively positive potential; a first power amplifier having an output terminal and including an input transistor having a control electrode and input and output current electrodes; a second power amplifier having an output terminal and including an input transistor having a control electrode and input and output current electrodes; means connecting a source of potential across said input and output current electrodes of said first and second power amplifier input transistors; means connecting said first transistor output electrode to said first power amplifier input transistor control electrodes; means connecting said second transistor output electrode to said second power amplifier input transistor control electrode; a first zener diode and a third resistor connected in series between said first power amplifier input transistor control electrode and said source of relatively negative potential; a second zener diode and a fourth resistor connected in series between said second power amplifier input transistor control electrode and said source of relatively negative potential; first diode means connecting said second power amplifier output terminal to the junction between said first zener diode and said third resistor; and second diode means connecting said first power amplifier output terminal to the junction between said second zener diode and said fourth resistor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-06-06 | 1975-12-06 | 1976-06-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-06-06 | 1979-12-06 | 1980-06-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-06-06 | 1983-12-06 | 1984-06-06 | $7700.00 | Window Closed / Lapsed |