US3668426A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Differential pulse height discriminator
Assignee: Western Atlas International Inc
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Filing: 1969-07-23
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Granted: 1972-06-06
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Expires: 1989-07-23
Abstract
Abstract A pair of transistors are each normally biased to saturation, one more strongly than the other. A tunnel diode connected between the collectors, respectively, produces an output voltage only when one of the transistors is driven out of saturation, but not when both transistors are non-saturated. Neither transistor is taken out of saturation until the signal pulse input reaches a certain predetermined amplitude. When the input pulse reaches a second predeterminde amplitude, both transistors are taken out of saturation. Thus, only pulses of amplitudes within a given range produce output signals. In an alternative embodiment, a single transistor replaces the tunnel diode. In another embodiment, the tunnel diode is replaced by a second differential pair of transistors.
Inventors
- 👤 Richard B Culver
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 18:10
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/22
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
115 words
A circuit for providing differential discrimination as to pulse amplitude comprising: a. a first transistor biased to a first conductive state of saturation; b. a second transistor biased to a second conductive state of saturation, said second transistor being biased to saturation more heavily than said first transistor; c. input circuit means connected to each of said transistors whereby input pulses can be applied thereto to affect the conductive states of said transistors; and d. detection means connected between said transistors for providing a signal output responsive to said first transistor being removed from saturation by an input pulse having an amplitude within a predetermined range of amplitudes while said second transistor remains in saturation.
Claim 2
Dependent Claim
115 words
A circuit for providing differential discrimination as to pulse amplitude comprising: a. a first transistor biased to a first conductive state of saturation; b. a second transistor biased to a second conductive state of saturation, said second transistor being biased to saturation more heavily than said first transistor; c. input circuit means connected to each of said transistors whereby input pulses can be applied thereto to affect the conductive states of said transistors; and d. detection means connected between said transistors for providing a signal output responsive to said first transistor being removed from saturation by an input pulse having an amplitude within a predetermined range of amplitudes while said second transistor remains in saturation.
Claim 3
Dependent Claim
14 words
The circuit according to claim 1 wherein said detection means comprises a tunnel diode.
Claim 4
Dependent Claim
35 words
The circuit according to claim 2 including in addition thereto a resistor and an inductor connected in series with said tunnel diode to provide pulse shaping of the signal output developed across said tunnel diode.
Claim 5
Dependent Claim
28 words
The circuit according to claim 1 wherein said detection means comprises a third transistor arranged to be conductive responsive to said first transistor being taken out of saturation.
Claim 6
Dependent Claim
58 words
The circuit according to claim 1 wherein said detection means comprises a third and a fourth transistor together connected as a differential pair, said third transistor being arranged to be conductive responsive to said first transistor being taken out of saturation while said fourth transistor remains non-conductive responsive to said second transistor remaining in a state of saturation.
Claim 7
Dependent Claim
113 words
A circuit for providing differential discrimination as to pulse amplitude comprising: a. a first transistor biased to a first conductive state of saturation; b. a second transistor biased to a second conductive state of saturation, said second transistor being biased to saturation more heavily than said first transistor; c. input circuit means connected to each of said transistors whereby input pulses can be applied thereto, whereby an input pulse can either cause each of the transistors to remain in saturation, or cause only the first transistor to be taken out of saturation, or cause each of the transistors to be taken out of saturation; and d. coincidence-indicative detection means connected between said transistors.
Claim 8
Dependent Claim
113 words
A circuit for providing differential discrimination as to pulse amplitude comprising: a. a first transistor biased to a first conductive state of saturation; b. a second transistor biased to a second conductive state of saturation, said second transistor being biased to saturation more heavily than said first transistor; c. input circuit means connected to each of said transistors whereby input pulses can be applied thereto, whereby an input pulse can either cause each of the transistors to remain in saturation, or cause only the first transistor to be taken out of saturation, or cause each of the transistors to be taken out of saturation; and d. coincidence-indicative detection means connected between said transistors.
Claim 9
Dependent Claim
14 words
The circuit according to claim 6 wherein said detection means comprises a tunnel diode.
Claim 10
Dependent Claim
35 words
The circuit according to claim 7 including in addition thereto a resistor and an inductor connected in series with said tunnel diode to provide pulse shaping of the signal output developed across said tunnel diode.
Claim 11
Dependent Claim
28 words
The circuit according to claim 6 wherein said detection means comprises a third transistor arranged to be conductive responsive to said first transistor being taken out of saturation.
Claim 12
Dependent Claim
58 words
The circuit according to claim 6 wherein said detection means comprises a third and a fourth transistor together connected as a differential pair, said third transistor being arranged tO be conductive responsive to said first transistor being taken out of saturation while said fourth transistor remains non-conductive responsive to said second transistor remaining in a state of saturation.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-06-06 | 1975-12-06 | 1976-06-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-06-06 | 1979-12-06 | 1980-06-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-06-06 | 1983-12-06 | 1984-06-06 | $7700.00 | Window Closed / Lapsed |