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US3667041A Expired / Lapsed US ⏱️ 0.0 years remaining

Automatic zero circuitry for indicating devices

Assignee: BLH Electronics Inc
•
Filing: 1969-12-04
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Granted: 1972-05-30
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Expires: 1989-12-04
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Abstract

Abstract Automatic zero circuitry for low-level signal indicating devices is provided which includes a capacitor at the output of an amplifier for storing a charge, during a given period of time, equal to the drift or offset voltage of the amplifier such that during a measuring period of time, the indicating device will give a true and correct reading. A dual slope integrator in combination with a plurality of field-effect-transistors enables the proper time periods for the storing and reading operations described above.

Inventors

  • 👤 Donald A Senour

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-24 15:30
CPC Classifications
G; G01; G01R; G01R1/00; G01R1/28

Claims Analysis

Total Claims: 2
Claim 1
Independent Claim 285 words
Automatic zero circuitry for eliminating errors due to DC amplifier offset voltage comprising a DC-excited Wheatstone bridge arrangement including strain gage elements in the arms thereof and producing low-level DC output signals as the result of unbalance thereof, measuring and indicating means including a dual-slope integrator, a DC amplifier for amplifying said output signals and applying related DC voltage signals to said dualslope integrator, a capacitor for storing voltage equal to the offset voltage of said amplifier, and switch means for periodically interrupting input to said amplifier while simultaneously connecting said capacitor for storage of said voltage during first periods and for periodically connecting the said low-level DC output signals to said amplifier while simultaneously applying to said dual-slope integrator the voltage across said capacitor in opposing relation to said DC voltage signals from said amplifier during second periods alternating with said first periods, said switch means comprising a first field-effect-transistor switch connected in series with said input to said amplifier, a second field-effect-transistor switch connected across said input to said amplifier, and a third fieldeffect-transistor switch connected between said capacitor and ground potential, said dual-slope integrator including means which, during said second periods, integrates up the voltage signals from said amplifier with the voltage across said capacitor subtracted therefrom, and which integrates down with respect to a reference input and passes through a dead time period during periods including said first periods, said first switch being off and said second and third switches being on during said first periods anD said first switch being on and said second and third switches being off during said second periods, whereby error due to said DC amplifier offset voltage is eliminated from measurements by said dual-slope integrator.
Claim 2
Dependent Claim 285 words
Automatic zero circuitry for eliminating errors due to DC amplifier offset voltage comprising a DC-excited Wheatstone bridge arrangement including strain gage elements in the arms thereof and producing low-level DC output signals as the result of unbalance thereof, measuring and indicating means including a dual-slope integrator, a DC amplifier for amplifying said output signals and applying related DC voltage signals to said dualslope integrator, a capacitor for storing voltage equal to the offset voltage of said amplifier, and switch means for periodically interrupting input to said amplifier while simultaneously connecting said capacitor for storage of said voltage during first periods and for periodically connecting the said low-level DC output signals to said amplifier while simultaneously applying to said dual-slope integrator the voltage across said capacitor in opposing relation to said DC voltage signals from said amplifier during second periods alternating with said first periods, said switch means comprising a first field-effect-transistor switch connected in series with said input to said amplifier, a second field-effect-transistor switch connected across said input to said amplifier, and a third fieldeffect-transistor switch connected between said capacitor and ground potential, said dual-slope integrator including means which, during said second periods, integrates up the voltage signals from said amplifier with the voltage across said capacitor subtracted therefrom, and which integrates down with respect to a reference input and passes through a dead time period during periods including said first periods, said first switch being off and said second and third switches being on during said first periods anD said first switch being on and said second and third switches being off during said second periods, whereby error due to said DC amplifier offset voltage is eliminated from measurements by said dual-slope integrator.

References Cited (Backward Citations)

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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1975-05-30 1975-11-29 1976-05-30 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1979-05-30 1979-11-29 1980-05-30 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1983-05-30 1983-11-29 1984-05-30 $7700.00 Window Closed / Lapsed

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