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US3666972A Expired / Lapsed US ⏱️ 0.0 years remaining

Delay device

Assignee: US Philips Corp
•
Filing: 1970-11-12
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Granted: 1972-05-30
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Expires: 1990-11-12
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Abstract

Abstract A capacitive delay device comprising a sequence of capacitances which have been interconnected by the main current path of at least one transistor, a feedback path being provided between the output electrode of at least one transistor and the input electrode thereof.

Inventors

  • 👤 Frederik L J Sangster

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-29 20:46
CPC Classifications
G; G11; G11C; G11C27/00; G11C27/04

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 187 words
A device for delaying a train of signal samples of an electrical signal, comprising a plurality of interconnected stages, each stage comprising a transistor having a control input and a main conduction path comprising a signal input and a signal output, wherein current through the main conduction path is a function of voltage between the control input and the signal input thereof, each stage further comprising a capacitor and first means for connecting the capacitor across the control input and signal output of the transistor, the device further comprising second means for serially connecting the main conduction paths of the transistors in all of the stages, means connected to the control inputs of the transistors in all of the stages for receiving switching pulses having a magnitude sufficient to render alternate transistors of the device conducting, and feedback means connecting the signal output of a transistor in a selected stage of the device to the signal input of the transistor in the selected stage for feeding a portion of the voltage on the capacitor of the selected stage to the signal input terminal of the associated transistor.
Claim 2
Independent Claim 187 words
A device for delaying a train of signal samples of an electrical signal, comprising a plurality of interconnected stages, each stage comprising a transistor having a control input and a main conduction path comprising a signal input and a signal output, wherein current through the main conduction path is a function of voltage between the control input and the signal input thereof, each stage further comprising a capacitor and first means for connecting the capacitor across the control input and signal output of the transistor, the device further comprising second means for serially connecting the main conduction paths of the transistors in all of the stages, means connected to the control inputs of the transistors in all of the stages for receiving switching pulses having a magnitude sufficient to render alternate transistors of the device conducting, and feedback means connecting the signal output of a transistor in a selected stage of the device to the signal input of the transistor in the selected stage for feeding a portion of the voltage on the capacitor of the selected stage to the signal input terminal of the associated transistor.
Claim 3
Dependent Claim 84 words
A device as claimed in claim 1, further comprising a first resistor serially connected with the capacitor of a stage preceeding the selected stage and the signal input of the transistor in the selected stage, a second resistor connected to the first resistor and the capacitor of the stage preceeding the selected stage and a non-inverting amplifier having an output connected through the second resistor to the first resistor and an input connected to the signal output of the transistor in the selected stage.
Claim 4
Dependent Claim 34 words
A device as claimed in claim 2, wherein the non-inverting amplifier comprises a field effect transistor, the drain and gate electrodes of which form the output and input respectively of the non-inverting amplifier circuit.
Claim 5
Dependent Claim 20 words
A device as claimed in claim 1, wherein a substantial portion of the device is integrated in a semiconductor body.

References Cited (Backward Citations)

US3431433A Cited
US3395292A Cited
US3474260A Cited
US3546490A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1975-05-30 1975-11-29 1976-05-30 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1979-05-30 1979-11-29 1980-05-30 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1983-05-30 1983-11-29 1984-05-30 $7700.00 Window Closed / Lapsed

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