Approximation analog to digital converter

Claim 2

An analog to digital converter comprising the combination of an integrating circuit having an input and an output; means for applying an analog signal to the input of said circuit for a predetermined interval of time to cause the output of said circuit to ramp away from a datum level; means for subsequently applying additional signals to the input of said integrating circuit to reduce the level of the output of said circuit toward said datum level in a succession of voltage ramps, each of said ramps including a plurality of fixed magnitude voltage steps, each of said ramps after the first having steps which are equal to the steps in the preceding ramp divided by a factor N, resulting in a mean slope equal to the slope of the preceding ramp divided by a factor N, said means for subsequently applying additional signals including means for reversing the direction of the ramp voltage from one voltage ramp to the next by reversing polarity of said additional signals; means for generating clock pulses in timed relationship with said voltage ramps; means responsive to the output of said integrating circuit for terminating each said voltage ramp when the output of said integrating circuit is reStored to within a preselected approximation of said datum level and means for counting the number of clock pulses occurring from the beginning of each voltage ramp to the termination thereof.

Claim 3

An analog to digital converter according to claim 1 and further comprising means for individually indicating numbers corresponding to the numbers of clock pulses counted during each of said voltage ramps.

Claim 4

An analog to digital converter according to claim 1, wherein the ranges are decade ranges and N is 10.

Claim 5

An analog to digital converter according to claim 1, wherein said means for subsequently applying additional signals are arranged to scale the magnitude of said clock pulses from ramp to ramp by said factor N and to apply said scaled clock pulses to said integrating circuit to generate staircase ramps.

Claim 6

An analog to digital converter comprising the combination of an integrating circuit having an input and an output; means for applying an analog input signal to the input of said circuit for a predetermined interval of time to cause the output of said circuit to ramp away from a datum level; means for subsequently applying additional signals to the input of said integrating circuit to reduce the level of the output of said circuit toward said datum level in a succession of voltage ramps, each of said ramps including a plurality of fixed magnitude voltage steps, each of said ramps after the first having steps which are smaller than the steps in the preceding ramp divided by a factor N, resulting in a mean slope equal to the slope of the preceding ramp divided by a factor N, said means for subsequently applying additional signals including means for reversing the direction of the ramp voltage from one voltage ramp to the next by reversing the polarity of said additional signals; means for generating clock pulses in timed relationship with said voltage ramps; means responsive to the output of said integrating circuit for terminating each said voltage ramp when the output of said integrating circuit is restored to within a preselected approximation of said datum level, said means responsive to the output of said integrating circuit including means for terminating at least said first voltage ramp after that clock pulse which occurs next after said integrating circuit output overshoots said datum level; and means for counting the number of clock pulses occurring from the beginning of each voltage ramp to the termination thereof.

Claim 7

An analog to digital converter comprising the combination of an integrating circuit having an input and an output; means for applying an analog input signal to the input of said circuit for a predetermined interval of time to cause the output of said circuit to ramp away from a datum level; means for subsequently applying additional signals to the input of said integrating circuit to reduce the level of the output of said circuit toward said datum level in a succession of voltage ramps, each of said ramps including a plurality of fixed magnitude voltage steps, each of said ramps after the first having steps which are smaller than the steps in the preceding ramp divided by a factor N, resulting in a mean slope equal to the slope of the preceding ramp divided by a factor N, said means for subsequently applying additional signals including means for reversing the direction of the ramp voltage from one voltage ramp to the next by reversing the polarity of said additional signals; means for generating clock pulses in timed relationship with said voltage ramps; means responsive to the output of said integrating circuit for terminating each said voltage ramp when the output of said integrating circuit is restored to within a preselected approximation of said datum level, said means responsive to the output of said integrating circuit including means for terminating at least said first voltage ramp after that clock pulse which occurs next after said integrating circuit output overshoots said datum level; and means for counting the number of clock pulses occurring from the beginning of each voltage ramp to the termination thereof.

Claim 8

An analog to digital converter comprising the combination of an integrating circuit having an input and an output; means for applying an analog input signal to the input of said circuit for a predetermined interval of time to cause the output of said circuit to ramp away from a datum level; means for subsequently applying additional signals to the input of said integrating circuit to reduce the level of the output of said circuit toward a datum level in a succession of voltage ramps, each of said ramps including a plurality of fixed magnitude voltage steps, each of said ramps after the first having steps which are smaller than the steps in the preceding ramp divided by a factor N, resulting in a mean slope equal to the slope of the preceding ramp divided by a factor N; means for generating clock pulses in timed relationship with said voltage ramps; means responsive to the output of said integrating circuit to terminate each said voltage ramp when the output of said integrating circuit is restored to within a preselected approximation of said datum level and means for counting the number of clock pulses occurring from the beginning of each voltage ramp to the termination thereof, and means for individually indicating numbers corresponding to the numbers of clock pulses counted during each of said voltage ramps, wherein said means for indicating indicates one number less than the number in the counter for an odd-numbered voltage ramp and further indicates N minus the number in the counter for an even-numbered voLtage ramp.

Claim 9

An analog to digital converter comprising the combination of an integrating circuit having an input and an output; means for applying an analog input signal to the input of said circuit for a predetermined interval of time to cause the output of said circuit to ramp away from a datum level; means for subsequently applying additional signals to the input of said integrating circuit to reduce the level of the output of said circuit toward a datum level in a succession of voltage ramps, each of said ramps including a plurality of fixed magnitude voltage steps, each of said ramps after the first having steps which are smaller than the steps in the preceding ramp divided by a factor N, resulting in a mean slope equal to the slope of the preceding ramp divided by a factor N; means for generating clock pulses in timed relationship with said voltage ramps; means responsive to the output of said integrating circuit to terminate each said voltage ramp when the output of said integrating circuit is restored to within a preselected approximation of said datum level and means for counting the number of clock pulses occurring from the beginning of each voltage ramp to the termination thereof, and means for individually indicating numbers corresponding to the numbers of clock pulses counted during each of said voltage ramps, wherein said means for indicating indicates one number less than the number in the counter for an odd-numbered voltage ramp and further indicates N minus the number in the counter for an even-numbered voLtage ramp.

Claim 10

An analog to digital converter comprising, signal integrating means and means for supplying an analog input signal to said integrating means for a fixed time interval to cause said integrating means produces an output signal which is proportional to the time integral of the analog input signal supplied thereto and which departs from a threshold signal level in one direction, means coupled to the signal integrating means for returning the output signal at one rate of speed to a level which overshoots said threshold level, means for timing this return of the output signal to provide a first, high numerical significance digit of a digital representation of the analog signal magnitude, means for returning the overshooting output signal to said threshold level at a reduced rate of speed, and means for timing this return of the overshooting output signal to provide a second, lower significance digit of said digital representation.

Claim 11

An analog to digital converter comprising, signal integrating means and means for supplying an analog input signal to said integrating means for a fixed time interval to cause said integrating means produces an output signal which is proportional to the time integral of the analog input signal supplied thereto and which departs from a threshold signal level in one direction, means coupled to the signal integrating means for returning the output signal at one rate of speed to a level which overshoots said threshold level, means for timing this return of the output signal to provide a first, high numerical significance digit of a digital representation of the analog signal magnitude, means for returning the overshooting output signal to said threshold level at a reduced rate of speed, and means for timing this return of the overshooting output signal to provide a second, lower significance digit of said digital representation.

Claim 12

An analog to digital converter comprising an integrating circuit having an input and an output and means for applying an analog input signal to the integrating circuit input for a fixed time interval whereupon said integrating circuit output produces an output signal which departs in one direction from a threshold signal level and is characterized as having a slope proportional to the magnitude of said input signal, means coupled to said integrating circuit input for subsequent applying thereto a first reference signal having a polarity opposite that of said input signal and a magnitude sufficient to cause the integrating circuit output signal to first return to and then overshoot said threshold signal level in the return direction, means including a second reference signal having the same polarity as said input signal and a magnitude which is a fraction of the first reference signal magnitude for returning the overshooting integrating circuit output signal to said threshold signal level, and means for individually clocking the different times required to return the integrating circuit output signal to said threshold signal level to provide first and second digits of decreasing numerical signal order to provide a digital representation of the input signal magnitude.

Claim 13

An analog to digital converter comprising an integrating circuit having an input and an output and means for applying an analog input signal to the integrating circuit input for a fixed time interval whereupon said integrating circuit output produces an output signal which departs in one direction from a threshold signal level and is characterized as having a slope proportional to the magnitude of said input signal, means coupled to said integrating circuit input for subsequent applying thereto a first reference signal having a polarity opposite that of said input signal and a magnitude sufficient to cause the integrating circuit output signal to first return to and then overshoot said threshold signal level in the return direction, means including a second reference signal having the same polarity as said input signal and a magnitude which is a fraction of the first reference signal magnitude for returning the overshooting integrating circuit output signal to said threshold signal level, and means for individually clocking the different times required to return the integrating circuit output signal to said threshold signal level to provide first and second digits of decreasing numerical signal order to provide a digital representation of the input signal magnitude.