US3665405A — Multiplexer

Claim 1

Independent Claim 205 words

A multiplexer comprising a timing generator responsive to incoming high speed clock and frame signals to produce submultiple clock and frame signals at the required low speed data rate, and an encoder adapted to be connected to a plurality of low speeD data sources, said timing generator including counting means driven by said incoming clock pulses for producing low speed clock pulses, switch means connected to said counting means for selecting one of a series of submultiple low speed rates for said counting means, a frame counter connected to the source of high speed frame signals, means driving the frame counter with said low speed clock pulses to produce low speed frame pulses, and said encoder comprising a parallel to serial converter with a plurality of parallel input terminals for said low speed data sources, an input clock terminal and a high speed data output terminal, said encoder also including means for applying low speed clock and frame signals from the timing generator to the parallel to serial converter to define a frame of low speed data, and means for applying high speed clock pulses to the encoder to advance frames of data from the low speed sources to the high speed data output terminals.

Claim 2

Dependent Claim 205 words

A multiplexer comprising a timing generator responsive to incoming high speed clock and frame signals to produce submultiple clock and frame signals at the required low speed data rate, and an encoder adapted to be connected to a plurality of low speeD data sources, said timing generator including counting means driven by said incoming clock pulses for producing low speed clock pulses, switch means connected to said counting means for selecting one of a series of submultiple low speed rates for said counting means, a frame counter connected to the source of high speed frame signals, means driving the frame counter with said low speed clock pulses to produce low speed frame pulses, and said encoder comprising a parallel to serial converter with a plurality of parallel input terminals for said low speed data sources, an input clock terminal and a high speed data output terminal, said encoder also including means for applying low speed clock and frame signals from the timing generator to the parallel to serial converter to define a frame of low speed data, and means for applying high speed clock pulses to the encoder to advance frames of data from the low speed sources to the high speed data output terminals.

Claim 3

Dependent Claim 43 words

The combination in accordance with claim 1 wherein said encoder includes controllable delay means between the source of low speed clock and frame signals and the parallel to serial converter whereby outgoing data may be delay time compensated for proper time slot transmission.

Claim 4

Dependent Claim 16 words

The combination in accordance with claim 2 including switching logic means for selecting the delay compensation.

Claim 5

Dependent Claim 16 words

The combination in accordance with claim 2 wherein said controllable delay means comprises a shift register.

Claim 6

Dependent Claim 19 words

The combination in accordance with claim 1 wherein the utilization device comprises at least one similar data rate multiplexer.

Claim 7

Dependent Claim 54 words

The combination in accordance with claim 1 including a decoder comprising a serial to parallel converter, means applying high speed data in serial to said converter, and means applying low speed frame and clock pulses to said converter to discharge data in parallel to low speed utilization devices at the low speed frame rate.

Claim 8

Dependent Claim 81 words

The combination in accordance with claim 1 including a decoder adapted to be connected to a plurality of low speed data utilization devices, said decoder comprising a serial to parallel converter including input terminals for serial input of high speed data and high speed clock pulses to advance data within the serial to parallel converter, means for applying low speed clock and frame pulses to said serial to parallel converter to read out low speed data in a plurality of channels.

Claim 9

Dependent Claim 44 words

The combination in accordance with claim 1 wherein a plurality of similar multiplexers are connected to respective output terminals of the serial to parallel converter and including means applying low speed frame and clock pulses from said multiplexer to said plurality of similar multiplexers.

Claim 10

Dependent Claim 139 words

A data rate changer comprising: a storage memory; a read address counter; means for introducing data into said memory at an incoming frame rate; means for generating a read drive signal from the incoming data rate; said last means comprising; a phase locked loop circuit including a mixer, a low pass filter and a voltage controlled oscillator connected in loop configuration; means applying a clock signal derived from incoming data to the mixer of said phase locked loop circuit; means for dividing the output of the voltage controlled oscillator by an integer P; means for applying the divided output of the voltage controlled oscillator to the mixer; means dividing the output of the voltage controlled oscillator by a factor Q; and means for applying said last output to the read address counter as the read signal to the memory.

Claim 11

Dependent Claim 139 words

A data rate changer comprising: a storage memory; a read address counter; means for introducing data into said memory at an incoming frame rate; means for generating a read drive signal from the incoming data rate; said last means comprising; a phase locked loop circuit including a mixer, a low pass filter and a voltage controlled oscillator connected in loop configuration; means applying a clock signal derived from incoming data to the mixer of said phase locked loop circuit; means for dividing the output of the voltage controlled oscillator by an integer P; means for applying the divided output of the voltage controlled oscillator to the mixer; means dividing the output of the voltage controlled oscillator by a factor Q; and means for applying said last output to the read address counter as the read signal to the memory.

Claim 12

Dependent Claim 197 words

A data multiplexer including a high speed input terminal, and a high and low speed output terminal for serial connection in a data transmission system including a source of high speed serial data comprising: a multistage counter for counting at least one frame of high speed clock pulse; buffer sTorage means for storing incoming high speed data a pair of data select logic means each under the control of said counter, one of said data selected logic means being operative to connect the high speed data input terminal of said multiplexer to the high speed data output terminal of said multiplexer to pass high speed serial data through said multiplexer; the second of said data select logic means being connected to said high speed data input terminal of said multiplexer and to said buffer storage means for selectively introducing high speed serial data into said buffer storage means; means responsive to incoming frame and clock pulses for producing low speed frame and clock pulses; means applying said low speed frame and clock pulses to said buffer storage means to discharge data in said storage means at low speed through said low speed data terminal of said multiplexer.

Claim 13

Dependent Claim 197 words

A data multiplexer including a high speed input terminal, and a high and low speed output terminal for serial connection in a data transmission system including a source of high speed serial data comprising: a multistage counter for counting at least one frame of high speed clock pulse; buffer sTorage means for storing incoming high speed data a pair of data select logic means each under the control of said counter, one of said data selected logic means being operative to connect the high speed data input terminal of said multiplexer to the high speed data output terminal of said multiplexer to pass high speed serial data through said multiplexer; the second of said data select logic means being connected to said high speed data input terminal of said multiplexer and to said buffer storage means for selectively introducing high speed serial data into said buffer storage means; means responsive to incoming frame and clock pulses for producing low speed frame and clock pulses; means applying said low speed frame and clock pulses to said buffer storage means to discharge data in said storage means at low speed through said low speed data terminal of said multiplexer.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1975-05-23	1975-11-22	1976-05-23	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1979-05-23	1979-11-22	1980-05-23	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	1983-05-23	1983-11-22	1984-05-23	$7700.00	Window Closed / Lapsed

Multiplexer

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