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US3665221A
Expired / Lapsed
US
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Transistor bridge rectifier circuit
Assignee: AT&T Inc
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Filing: 1970-10-12
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Granted: 1972-05-23
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Expires: 1990-10-12
Abstract
Abstract The collectors and emitters of two pairs of complementary transistors are interconnected to form a bridge circuit while their bases are connected in a forward biasing sense to a directcurrent source. An alternating-current wave applied between one set of opposing corners of the bridge circuit causes a full wave rectified wave to appear between the remaining corners.
Inventors
- 👤 Noble Ervin Wickliff
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 19:50
CPC Classifications
H; H02; H02M; H02M7/00; H02M7/02; H02M7/04; H02M7/12; H02M7/21; H02M7/217; H02M7/219; H02M7/2195; Y; Y02; Y02B; Y02B70/00; Y02B70/10
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
170 words
In combination, first and second NPN transistors each having an emitter, a base and a collector, first and second PNP transistors each having an emitter, a base and a collector, a pair of input terminals for receiving an alternating current voltage, a substantially zero impedance conducting path connected between one of said input terminals and said emitters of said first NPN and PNP transistors, a substantially zero impedance conducting path connected between the other of said input terminals and said emitters of said second NPN and PNP transistors, a pair of output terminals, a substantially zero impedance conducting path connected between one of said output terminals and said collectors of said NPN transistors, a substantially zero impedance conducting path connected between the other of said output terminals and said collectors of said PNP transistors, a single direct-current source, and resistance means connected between said direct current source and said bases to forward bias the base-emitter paths of said transistors in the absence of any voltage applied between said input terminals.
Claim 2
Dependent Claim
170 words
In combination, first and second NPN transistors each having an emitter, a base and a collector, first and second PNP transistors each having an emitter, a base and a collector, a pair of input terminals for receiving an alternating current voltage, a substantially zero impedance conducting path connected between one of said input terminals and said emitters of said first NPN and PNP transistors, a substantially zero impedance conducting path connected between the other of said input terminals and said emitters of said second NPN and PNP transistors, a pair of output terminals, a substantially zero impedance conducting path connected between one of said output terminals and said collectors of said NPN transistors, a substantially zero impedance conducting path connected between the other of said output terminals and said collectors of said PNP transistors, a single direct-current source, and resistance means connected between said direct current source and said bases to forward bias the base-emitter paths of said transistors in the absence of any voltage applied between said input terminals.
Claim 3
Dependent Claim
168 words
In combination, first and second pairs of NPN and PNP complementary transistors where each transistor has an emitter, a base and a collector, a pair of input terminals, a pair of output terminals, a first substantially zero impedance conducting path connecting one of said input terminals to said emitters of said first pair of complementary transistors, a second substantially zero impedance conducting path connecting the other of said input terminals to said emitters of said second pair of complementary transistors, a third substantially zero impedance conducting path connecting one of said output terminals to said collectors of said NPN transistors in said pairs of complementary transistors, a fourth substantially zero impedance conducting path connecting the other of said output terminals to said collectors of said PNP transistors in said pairs of complementary transistors, a single direct-current source, and resistance means connected between said direct-current source and said bases to forward bias the base-emitter paths of said transistors in the absence of any voltage applied between said input terminals.
Claim 4
Dependent Claim
168 words
In combination, first and second pairs of NPN and PNP complementary transistors where each transistor has an emitter, a base and a collector, a pair of input terminals, a pair of output terminals, a first substantially zero impedance conducting path connecting one of said input terminals to said emitters of said first pair of complementary transistors, a second substantially zero impedance conducting path connecting the other of said input terminals to said emitters of said second pair of complementary transistors, a third substantially zero impedance conducting path connecting one of said output terminals to said collectors of said NPN transistors in said pairs of complementary transistors, a fourth substantially zero impedance conducting path connecting the other of said output terminals to said collectors of said PNP transistors in said pairs of complementary transistors, a single direct-current source, and resistance means connected between said direct-current source and said bases to forward bias the base-emitter paths of said transistors in the absence of any voltage applied between said input terminals.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-05-23 | 1975-11-22 | 1976-05-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-05-23 | 1979-11-22 | 1980-05-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-05-23 | 1983-11-22 | 1984-05-23 | $7700.00 | Window Closed / Lapsed |