Patent US3665103A successfully refreshed from Google Patents.
US3665103A
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US
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Synchronous frequency shift data transmission system in which opposite binary characterizations are transmitted as half cycles of a first carrier signal and as full cycles of a second carrier signal
Assignee: International Business Machines Corp
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Filing: 1969-12-16
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Granted: 1972-05-23
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Expires: 1989-12-16
Abstract
Abstract A data transmission system in which data to be transmitted is encoded using double frequency coding, the keying signal which defines the individual bit cells being in-phase with first and second carrier signals having frequencies equal to that of the keying signal frequency and twice that of the keying signal frequency. Opposite binary characterizations (''''zeros'''' and ''''ones'''') are respectively transmitted as a half-cycle of the first carrier signal or a full cycle of the second carrier signal within the appropriate bit cells, the synchronous relationship between the keying and carrier signals providing for bit cells of equal size and self-clocking. Encoded data is processed at the transmitting and receiving ends of a transmission line by circuitry which is transformer coupled to the line at both ends to provide isolation and minimize common mode noise and ground shift problems, and which is impedance matched to the line to provide high noise immunity.
Inventors
- 👤 Robert V Watkins
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 18:06
CPC Classifications
H; H04; H04L; H04L27/00; H04L27/10
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
439 words
An arrangement for encoding data for transmission over a transmission line, the data to be encoded appearing in the form of a data signal which is arbitrarily divided into a succession of substantially uniform bit cells and which assumes a high or low value within each bit cell to represent one or the other of opposite binary characterizations, comprising: means responsive to the data signal for generating an intermediate signal having a succession of bit cells corresponding to the bit cells of the data signal and a voltage which varies between zero and a selected value other than zero, the intermediate signal having a voltage transition between zero and the selected value at the leading and trailing edges of each bit cell in which the data signal assumes the low value and a voltage transition between zero and the selected value at the leading edge, center, and trailing edge of each bit cell in which the data signal assumes the high value; and means coupled between the intermediate signal generating means and the transmission line and responsive to the intermediate signal to generate a signal for transmission over the transmission line, the transmission signal having a succession of bit cells corresponding to the bit cells of the intermediate signal and a voltage which varies between opposite positive and negative voltages of substantially equal value, the transmission signal having a voltage transition between the opposite positive and negative voltages at various locations within the bit cells corresponding to the voltage transitions of the intermediate signal, the transmission signal generating means including first and second alternately conductive transistors coupled to respectively provide the opposite positive and negative voltages to the transmission line when conducting, a power supply, a transformer having a pair of primary windings and a secondary winding coupled to the transmission line, means coupling different ones of the pair of primary windings between the power supply and the first and second transistors, and means responsive to the intermediate signal for biasing the first transistor into conduction whenever the voltage of the intermediate signal assumes the selected value and for biasing the second transistor into conduction whenever the voltage of the intermediate signal assumes zero value, the biasing means including a third transistor coupled to be biased into nonconduction and conduction whenever the voltage of the first signal assumes zero value and the selected value respectively, and coupled to bias the first transistor into conduction when conducting, and a capacitor coupled to render the second transistor conductive when charging and to discharge through the third transistor and thereby prevent conduction of the second transistor whenever the third transistor is conducting.
Claim 2
Dependent Claim
439 words
An arrangement for encoding data for transmission over a transmission line, the data to be encoded appearing in the form of a data signal which is arbitrarily divided into a succession of substantially uniform bit cells and which assumes a high or low value within each bit cell to represent one or the other of opposite binary characterizations, comprising: means responsive to the data signal for generating an intermediate signal having a succession of bit cells corresponding to the bit cells of the data signal and a voltage which varies between zero and a selected value other than zero, the intermediate signal having a voltage transition between zero and the selected value at the leading and trailing edges of each bit cell in which the data signal assumes the low value and a voltage transition between zero and the selected value at the leading edge, center, and trailing edge of each bit cell in which the data signal assumes the high value; and means coupled between the intermediate signal generating means and the transmission line and responsive to the intermediate signal to generate a signal for transmission over the transmission line, the transmission signal having a succession of bit cells corresponding to the bit cells of the intermediate signal and a voltage which varies between opposite positive and negative voltages of substantially equal value, the transmission signal having a voltage transition between the opposite positive and negative voltages at various locations within the bit cells corresponding to the voltage transitions of the intermediate signal, the transmission signal generating means including first and second alternately conductive transistors coupled to respectively provide the opposite positive and negative voltages to the transmission line when conducting, a power supply, a transformer having a pair of primary windings and a secondary winding coupled to the transmission line, means coupling different ones of the pair of primary windings between the power supply and the first and second transistors, and means responsive to the intermediate signal for biasing the first transistor into conduction whenever the voltage of the intermediate signal assumes the selected value and for biasing the second transistor into conduction whenever the voltage of the intermediate signal assumes zero value, the biasing means including a third transistor coupled to be biased into nonconduction and conduction whenever the voltage of the first signal assumes zero value and the selected value respectively, and coupled to bias the first transistor into conduction when conducting, and a capacitor coupled to render the second transistor conductive when charging and to discharge through the third transistor and thereby prevent conduction of the second transistor whenever the third transistor is conducting.
Claim 3
Dependent Claim
38 words
The invention defined in claim 1 above, further including: means associated with the first transistor for biasing the first transistor into nonconduction independently of the third transistor whenever the first transistor conducts for a predetermined period of time.
Claim 4
Dependent Claim
64 words
The invention defined in claim 2 above, wherein the means for independently biasing the first transistor into nonconduction comprises: a coil; a pair of diodes; and means for coupling the serial combination of the coil and one of the diodes between base and emitter terminals of the first transistor and for coupling the other one of the diodes in parallel with the serial combination.
Claim 5
Dependent Claim
375 words
An arrangement for decoding data transmitted over a transmission line, the data to be decoded appearing in the form of a transmitted signal which is arbitrarily divided into a succession of substantially uniform bit cells and which has a transition between opposite positive and negative voltages of substantially equal value at the leading and trailing edges of each bit cell representing one binary characterization and a transition at the leading edge, center and trailing edge of each bit cell representing a binary characterization opposite the one binary characterization, comprising: means coupled to the transmission line and responsive to the transmitted signal for generating an intermediate signal having a succession of bit cells corresponding to the bit cells of the transmitted signal and a voltage which varies between zero and a selected value other than zero, the intermediate signal having a voltage transition between zero and the selected value at various locations within the bit cells corresponding to the voltage transitions of the transmitted signal, the intermediate signal generating means including first and second alternately conductive transistors, the first transistor providing the intermediate signal voltage with zero value when conducting and with the selected value when not conducting, a transformer having a primary winding coupled to the transmission line and a pair of secondary windings for providing a step-up voltage ratio, and means responsive to the transmitted signal for biasing the first transistor into conduction whenever the transmitted signal has the positive voltage and for biasing the second transistor into conduction whenever the transmitted signal has the negative voltage, the biasing means including a resistor and a capacitor coupled between the secondary windings and the first transistor, the value of the resistor being selected in accordance with the characteristic impedance of the line to provide impedance matching; and means responsive to the intermediate signal for generating a data signal having a succession of bit cells corresponding to the bit cells of the intermediate signal, the data signal assuming a high value within those bit cells in which the intermediate signal has a voltage transition at the leading edge, center and trailing edge and assuming a low value within those bit cells in which the intermediate signal has a voltage transition at the leading and trailing edges.
Claim 6
Dependent Claim
375 words
An arrangement for decoding data transmitted over a transmission line, the data to be decoded appearing in the form of a transmitted signal which is arbitrarily divided into a succession of substantially uniform bit cells and which has a transition between opposite positive and negative voltages of substantially equal value at the leading and trailing edges of each bit cell representing one binary characterization and a transition at the leading edge, center and trailing edge of each bit cell representing a binary characterization opposite the one binary characterization, comprising: means coupled to the transmission line and responsive to the transmitted signal for generating an intermediate signal having a succession of bit cells corresponding to the bit cells of the transmitted signal and a voltage which varies between zero and a selected value other than zero, the intermediate signal having a voltage transition between zero and the selected value at various locations within the bit cells corresponding to the voltage transitions of the transmitted signal, the intermediate signal generating means including first and second alternately conductive transistors, the first transistor providing the intermediate signal voltage with zero value when conducting and with the selected value when not conducting, a transformer having a primary winding coupled to the transmission line and a pair of secondary windings for providing a step-up voltage ratio, and means responsive to the transmitted signal for biasing the first transistor into conduction whenever the transmitted signal has the positive voltage and for biasing the second transistor into conduction whenever the transmitted signal has the negative voltage, the biasing means including a resistor and a capacitor coupled between the secondary windings and the first transistor, the value of the resistor being selected in accordance with the characteristic impedance of the line to provide impedance matching; and means responsive to the intermediate signal for generating a data signal having a succession of bit cells corresponding to the bit cells of the intermediate signal, the data signal assuming a high value within those bit cells in which the intermediate signal has a voltage transition at the leading edge, center and trailing edge and assuming a low value within those bit cells in which the intermediate signal has a voltage transition at the leading and trailing edges.
Claim 7
Dependent Claim
36 words
The invention defined in claim 4 above, further including a pair of diodes coupled in parallel between a source of reference potential and the first transistor, the diodes clamping the first transistor to prevent overdriving thereof.
Claim 8
Dependent Claim
35 words
The invention defined in claim 4 above, further including a transformer winding coupled to one of the pair of secondary windings, the transformer winding functioning as a secondary winding for transmission over the transmission line.
Claim 9
Dependent Claim
405 words
A synchronous frequency shift data transmission system for transmitting binary data over at least one transmission line, comprising: timing means including keying signal generating means for generating a succession of signal indications to define bit cells for the binary data to be transmitted, means for generating a clock pulse at the leading edge of each bit cell, and means for generating a data strobe pulse at the center of each bit cell; means coupled to the at least one transmission line and responsive to the timing means and to the binary data to be transmitted for transmitting a half-cycle of a first signal within those bit cells representing one binary characterization and for transmitting a full cycle of a second signal within those bit cells representing the opposite binary characterization, the first signal being in-phase with and having a frequency equal to that of the keying signal and the second signal bEing in-phase with and having a frequency equal to twice that of the keying signal, said means for transmitting including register means for temporarily storing binary data bits to be transmitted, a different data bit being advanced out of the register means upon the occurrence of each clock pulse, means responsive to the clock and data strobe pulses and to the data bits being advanced out of the register means for adding a data strobe pulse to the clock pulses in response to each advanced data bit which represents binary ''''one'''', bistable means coupled to change state in response to each clock pulse and to each added data strobe pulse, the bistable means providing an output voltage which varies between zero and a selected level in response to the state changes, and means responsive to the bistable means output voltage and coupled to the at least one transmission line for providing a positive voltage of selected value whenever the bistable means output voltage assumes the selected level and for providing a negative voltage of value substantially equal to the selected value whenever the bistable means output voltage is zero; means coupled to the at least one transmission line and responsive to the transmitted first and second signals for detecting the bit cells thereof; and means associated with the bit cell detecting means and responsive to the transmitted first and second signals for detecting the binary data within each bit cell in accordance with the particular one of the first and second signals transmitted therein.
Claim 10
Dependent Claim
405 words
A synchronous frequency shift data transmission system for transmitting binary data over at least one transmission line, comprising: timing means including keying signal generating means for generating a succession of signal indications to define bit cells for the binary data to be transmitted, means for generating a clock pulse at the leading edge of each bit cell, and means for generating a data strobe pulse at the center of each bit cell; means coupled to the at least one transmission line and responsive to the timing means and to the binary data to be transmitted for transmitting a half-cycle of a first signal within those bit cells representing one binary characterization and for transmitting a full cycle of a second signal within those bit cells representing the opposite binary characterization, the first signal being in-phase with and having a frequency equal to that of the keying signal and the second signal bEing in-phase with and having a frequency equal to twice that of the keying signal, said means for transmitting including register means for temporarily storing binary data bits to be transmitted, a different data bit being advanced out of the register means upon the occurrence of each clock pulse, means responsive to the clock and data strobe pulses and to the data bits being advanced out of the register means for adding a data strobe pulse to the clock pulses in response to each advanced data bit which represents binary ''''one'''', bistable means coupled to change state in response to each clock pulse and to each added data strobe pulse, the bistable means providing an output voltage which varies between zero and a selected level in response to the state changes, and means responsive to the bistable means output voltage and coupled to the at least one transmission line for providing a positive voltage of selected value whenever the bistable means output voltage assumes the selected level and for providing a negative voltage of value substantially equal to the selected value whenever the bistable means output voltage is zero; means coupled to the at least one transmission line and responsive to the transmitted first and second signals for detecting the bit cells thereof; and means associated with the bit cell detecting means and responsive to the transmitted first and second signals for detecting the binary data within each bit cell in accordance with the particular one of the first and second signals transmitted therein.
Claim 11
Dependent Claim
340 words
A synchronous frequency shift data transmission system for transmitting binary data over at least one transmission line, comprising: timing means including keying signal generating means for generating a succession of signal indications to define bit cells for the binary data to be transmitted; means coupled to the at least one transmission line and responsive to the timing means and to the binary data to be transmitted for transmitting a half-cycle of a first signal within those bit cells representing one binary characterization and for transmitting a full cycle of a second signal within those bit cells representing the opposite binary characterization, the first signal being in-phase with and having a frequency equal to that of the keying signal and the second signal being in-phase with and having a frequency equal to twice that of the keying signal, the first and second signals having voltages which vary between positive and negative voltages of substantially equal value; means responsive to the transmitted first and second signals for detecting the binary data within each bit cell in accordance with the particular one of the first and second signals transmitted therein, and including means responsive to the first and second signals for generating an intermediate signal, the voltage of which assumes a selected level whenever the voltage of the first or second signal is positive and zero whenever the voltage of the first or second signal is negative, means responsive to the intermediate signal for generating pulses of selected duration in time coincidence with the transitions thereof, register means, and means responsive to the pulses and coupled to the register means for passing those pulses which occur at the center of a bit cell to the register means to the exclusion of all other pulses; and means associated with the means for detecting the binary data and responsive to the transmitted first and second signals for detecting the bit cells thereof, said means including means responsive to the pulses for blocking those pulses which occur other than at the leading edges of bit cells.
Claim 12
Dependent Claim
340 words
A synchronous frequency shift data transmission system for transmitting binary data over at least one transmission line, comprising: timing means including keying signal generating means for generating a succession of signal indications to define bit cells for the binary data to be transmitted; means coupled to the at least one transmission line and responsive to the timing means and to the binary data to be transmitted for transmitting a half-cycle of a first signal within those bit cells representing one binary characterization and for transmitting a full cycle of a second signal within those bit cells representing the opposite binary characterization, the first signal being in-phase with and having a frequency equal to that of the keying signal and the second signal being in-phase with and having a frequency equal to twice that of the keying signal, the first and second signals having voltages which vary between positive and negative voltages of substantially equal value; means responsive to the transmitted first and second signals for detecting the binary data within each bit cell in accordance with the particular one of the first and second signals transmitted therein, and including means responsive to the first and second signals for generating an intermediate signal, the voltage of which assumes a selected level whenever the voltage of the first or second signal is positive and zero whenever the voltage of the first or second signal is negative, means responsive to the intermediate signal for generating pulses of selected duration in time coincidence with the transitions thereof, register means, and means responsive to the pulses and coupled to the register means for passing those pulses which occur at the center of a bit cell to the register means to the exclusion of all other pulses; and means associated with the means for detecting the binary data and responsive to the transmitted first and second signals for detecting the bit cells thereof, said means including means responsive to the pulses for blocking those pulses which occur other than at the leading edges of bit cells.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-05-23 | 1975-11-22 | 1976-05-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-05-23 | 1979-11-22 | 1980-05-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-05-23 | 1983-11-22 | 1984-05-23 | $7700.00 | Window Closed / Lapsed |