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US3663872A Expired / Lapsed US ⏱️ 0.0 years remaining

Integrated circuit lateral transistor

Assignee: NEC Corp
•
Filing: 1970-01-19
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Granted: 1972-05-16
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Expires: 1990-01-19
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Abstract

Abstract A lateral transistor serving as a minority transistor in an integrated circuit has a region buried in the base region and having an opposite conduction type to the base region.

Inventors

  • 👤 Takayuki Yanagawa

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-28 10:01
CPC Classifications
H; H10; H10D; H10D10/00; H10D10/60; H10D99/00; Y; Y10; Y10S; Y10S148/00; Y10S148/037; Y10S148/049; Y10S148/085; Y10S148/096; Y10S148/151

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 130 words
A lateral transistor comprising a semiconductor substrate of a first conductivity type, a base region of a second conductivity type opposite to that of said first conductivity type, said base region comprising a low-resistivity region formed in a surface portion of said substrate and a high-resistivity layer formed on said substrate, a buried region of said first conductivity type formed at the interface of said first low-resistivity region and said high-resistivity layer, whereby said buried region is completely surrounded by said base region, emitter and collector regions of said first conductivity type formed in the surface of said base region and overlying but isolated from said buried region, a single base electrode coupled to said base region, and emitter and collector electrodes coupled respectively to said emitter and collector regions.
Claim 2
Dependent Claim 130 words
A lateral transistor comprising a semiconductor substrate of a first conductivity type, a base region of a second conductivity type opposite to that of said first conductivity type, said base region comprising a low-resistivity region formed in a surface portion of said substrate and a high-resistivity layer formed on said substrate, a buried region of said first conductivity type formed at the interface of said first low-resistivity region and said high-resistivity layer, whereby said buried region is completely surrounded by said base region, emitter and collector regions of said first conductivity type formed in the surface of said base region and overlying but isolated from said buried region, a single base electrode coupled to said base region, and emitter and collector electrodes coupled respectively to said emitter and collector regions.
Claim 3
Dependent Claim 27 words
The transistor of claim 1, in which the ends of said buried region are in approximate alignment with the ends of said emitter and collector regions respectively.
Claim 4
Dependent Claim 25 words
The transistor of claim 2, further comprising a low-resistivity region of said second conductivity type formed in said base region and surrounding said emitter region.
Claim 5
Dependent Claim 25 words
The transistor of claim 1, further comprising a low-resistivity region of said second conductivity type formed in said base region and surrounding said emitter region.

References Cited (Backward Citations)

US3299281A Cited
US3284723A Cited
CH441512A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1975-05-16 1975-11-15 1976-05-16 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1979-05-16 1979-11-15 1980-05-16 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1983-05-16 1983-11-15 1984-05-16 $7700.00 Window Closed / Lapsed

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