Patent US3662377A successfully refreshed from Google Patents.
US3662377A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Triple-sample a/d converter
Assignee: International Business Machines Corp
•
Filing: 1970-04-30
•
Granted: 1972-05-09
•
Expires: 1990-04-30
Abstract
Abstract An analog-to-digital converter that eliminates dynamic coupling errors in a system where the measured signal and the reference signal are subject to such variations. This device sequentially samples an analog unknown voltage and a reference voltage and converts the sampled signals into digital information representative of the unknown voltage. Sampling and conversion is achieved in a three step process which alternates the reference and unknown signal inputs to an integrator and level holding circuits. The integrator output controls the duration of a digital counter which runs until the integrator output crosses a zero value. The result in the digital counter provides the binary value representative of the analog unknown signal. Dynamic coupling errors which occur during the reference and unknown signal sample times are eliminated by dividing the sample time of the unknown signal in two segments, a first sampling segment prior to sampling the reference signal, and a second sampling segment after the reference signal.
Inventors
- 👤 Herbert Dym
- 👤 Robert V Mazza
- 👤 Lawrence P Segar
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 14:06
CPC Classifications
G; G06; G06F; G06F3/00; G06F3/01; G06F3/03; G06F3/041; G06F3/044; H; H03; H03M; H03M1/00; H03M1/12; H03M1/50
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
187 words
An analog-to-digital converter comprising: signal input means for introducing an analog unknown voltage signal and a reference voltage signal to said converter; sampling means connected to said signal input means for selectively passing said unknown and reference signals at predetermined time intervals; integrator means connected to said sampling means for performing an integration on the signals that are passed under the control of said sampling means; said integrator means performing a first, second and third integration during a first, second and third integration interval respectively; pre-summation means connected to said integrator means for conditioning said integrator to sum the results of said first and third integrations; comparator means connected to said integrator means for Comparing the results of said second integration and the sum of said first and third integration; counter means connected to said comparator means for counting during the time that it takes said comparator to make an equal comparison detection; whereby said counting is terminated upon detection of an equal comparison and the resulting digital count in said counter means is linearly proportional to the ratio of unknown voltage signal to reference voltage signal.
Claim 2
Dependent Claim
187 words
An analog-to-digital converter comprising: signal input means for introducing an analog unknown voltage signal and a reference voltage signal to said converter; sampling means connected to said signal input means for selectively passing said unknown and reference signals at predetermined time intervals; integrator means connected to said sampling means for performing an integration on the signals that are passed under the control of said sampling means; said integrator means performing a first, second and third integration during a first, second and third integration interval respectively; pre-summation means connected to said integrator means for conditioning said integrator to sum the results of said first and third integrations; comparator means connected to said integrator means for Comparing the results of said second integration and the sum of said first and third integration; counter means connected to said comparator means for counting during the time that it takes said comparator to make an equal comparison detection; whereby said counting is terminated upon detection of an equal comparison and the resulting digital count in said counter means is linearly proportional to the ratio of unknown voltage signal to reference voltage signal.
Claim 3
Dependent Claim
110 words
The apparatus as defined in claim 1 wherein said pre-summation means comprises: a first hold means connected to said integrator means output for monitoring the output voltage of said integrator means during said first integration and for maintaining said output voltage; return gate means connected to said first hold means for reintroducing said maintained voltage to said integrator means after the second but prior to the third integration interval; whereby the reintroduction of the maintained voltage drives the integrator means output to the level of the output voltage following said first integration interval and said integrator means performing an effective summation by continuing to integrate during said third integration interval.
Claim 4
Dependent Claim
53 words
The apparatus as defined in claim 2 wherein said integrator means operates on said unknown voltage signal during said first and third integration intervals under the control of said sampling means and; said integrator means operates on said reference voltage signal during said second integration interval under the control of said sampling means.
Claim 5
Dependent Claim
95 words
The apparatus as defined in claim 3 further comprising a second hold means connected to said integrator means output for monitoring the output of said integrator means during said second integration interval and maintaining the output voltage level of said integrator; hold level gate means for reintroducing the said maintained voltage back to said integrator means; whereby the reintroduction of said maintained voltage occurs at the instant said counter means begins to count and said comparator means monitors said integrator output until a zero value is reached at which time said counter means is halted.
Claim 6
Dependent Claim
39 words
The apparatus as defined in claim 4 wherein said second integration is of the opposite polarity relative to said first and third integrations, whereby the integrator output voltage is returned to a zero value after said third integration interval.
Claim 7
Dependent Claim
16 words
The apparatus as defined in claim 5 wherein said comparator means is a zero detection circuit.
Claim 8
Dependent Claim
188 words
In a system for transducing analog voltage positional information into digital information linearly proportional to graphic position wherein the system consists of a tablet structure, a capacitive coupled stylus, sampling and detection means, analog-to-digital converter means, counter means and register output means, the improvement to said analog-to-digital converter means comprising: integrator means connected to said sampling means for performing an integration on signals that are passed under the control of said sampling means; said integrator means performing a first, second and third integration during a first, second and third integration interval, respectively; pre-summation means connected to said integrator means for conditioning said integrator to sum the results of said first and third integrations; comparison means connected to said integrator means for comparing the results of said second integration and the sum of said first and third integrations; whereby said counter means connected to said comparator means measures the time that it takes said comparator to make an equal comparison detection by terminating upon said detection and the resulting digital count in said counter means is linearly proportional to the ratio of unknown voltage signal to reference voltage signal.
Claim 9
Dependent Claim
188 words
In a system for transducing analog voltage positional information into digital information linearly proportional to graphic position wherein the system consists of a tablet structure, a capacitive coupled stylus, sampling and detection means, analog-to-digital converter means, counter means and register output means, the improvement to said analog-to-digital converter means comprising: integrator means connected to said sampling means for performing an integration on signals that are passed under the control of said sampling means; said integrator means performing a first, second and third integration during a first, second and third integration interval, respectively; pre-summation means connected to said integrator means for conditioning said integrator to sum the results of said first and third integrations; comparison means connected to said integrator means for comparing the results of said second integration and the sum of said first and third integrations; whereby said counter means connected to said comparator means measures the time that it takes said comparator to make an equal comparison detection by terminating upon said detection and the resulting digital count in said counter means is linearly proportional to the ratio of unknown voltage signal to reference voltage signal.
Claim 10
Dependent Claim
97 words
The apparatus as defined in claim 7 wherein said pre-summation means comprises; a first hold means connected To said integrator means output for monitoring the output voltage of said integrator means and maintaining said output voltage; return gate means connected to said first hold means for reintroducing said held voltage to said integrator means prior to the third integration interval; whereby the reintroduction of the held voltage drives the integrator means output to the value following said first integration interval and said integrator means performing an effective summation by continuing to integrate during said third integration interval.
Claim 11
Dependent Claim
53 words
The apparatus as defined in claim 8 wherein said integrator means operates on said unknown voltage signal during said first and third integration intervals under the control of said sampling means and; said integrator means operates on said reference voltage signal during said second integration interval under the control of said sampling means.
Claim 12
Dependent Claim
95 words
The apparatus as defined in claim 9 further comprising a second hold means connected to said integrator means output for monitoring the output of said integrator means during said second integration interval and maintaining the output voltage of said integrator; hold level gate means for reintroducing the said maintained voltage back to said integrator means; whereby the reintegration of said maintained voltage occurs at the instant said counter means begins to measure time and said comparator means monitors said integrator output until a zero value is reached at which time said counter means is halted.
Claim 13
Dependent Claim
39 words
The apparatus as defined in claim 9 wherein said second integration is of the opposite polarity relative to said first and third integrations output voltage, whereby the integrator is returned to a zero value after said third integration interval.
Claim 14
Dependent Claim
16 words
The apparatus as defined in claim 8 wherein said comparator means is a zero detection circuit.
Claim 15
Independent Claim
102 words
A method of converting an analog voltage signal to a digital signal representation comprising: performing a first integration on said analog voltage signal for a fixed period of time; performing a second integration on a reference voltage signal for a fixed period of time; performing a third integration on said analog voltage signal; combining the results of said first and third integrations; performing a fourth integration on the results of said second integration; measuring the amount of time needed for said fourth integration to reach a value equal to the sum of the results of said first integration and said third integration.
Claim 16
Independent Claim
102 words
A method of converting an analog voltage signal to a digital signal representation comprising: performing a first integration on said analog voltage signal for a fixed period of time; performing a second integration on a reference voltage signal for a fixed period of time; performing a third integration on said analog voltage signal; combining the results of said first and third integrations; performing a fourth integration on the results of said second integration; measuring the amount of time needed for said fourth integration to reach a value equal to the sum of the results of said first integration and said third integration.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-05-09 | 1975-11-08 | 1976-05-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-05-09 | 1979-11-08 | 1980-05-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-05-09 | 1983-11-08 | 1984-05-09 | $7700.00 | Window Closed / Lapsed |