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Patent US3662347A successfully refreshed from Google Patents.
US3662347A
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Signal compression and expansion system using a memory
Assignee: Boeing North American Inc
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Filing: 1970-03-11
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Granted: 1972-05-09
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Expires: 1990-03-11
Abstract
Abstract The compander system uses a register having a limited number of possible digital states, or counts, each weighted to represent a certain voltage. Each count is used to address a location in a memory which stores digital numbers having a different number of bit positions relative to the bit positions of the count in the register. Each number is weighted to represent a different voltage from the voltage value represented by the register count. An analog signal is generated in response to the stored digital number for comparison with the input signal even though the register count is changed as if the voltage represented by its count had been used for making the comparison. The process is continued until the signals are within the limits provided by the least significant digit of the stored number. The number in the register is then transmitted to the receiver where the digital signal is converted into an analog signal using an additional memory and register having a limited number of bit positions.
Inventors
- 👤 Duane C Fox
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 20:01
CPC Classifications
H; H04; H04B; H04B14/00; H04B14/02; H04B14/04; H04B14/046; H04B14/048
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
311 words
A signal companding system providing a change in data compression simultaneously with data conversion comprising: means for comparing an input analog signal and a variable analog reference signal until said input signal and said reference signal are approximately equal and providing a digital comparator output signal indicative of the difference between said input analog signal and said variable analog reference signal, clock generator and successive approximation logic means responsive to said digital comparator output signal, control register means responsive to a digital signal from said clock generator and successive approximation logic means for temporarily storing binary numbers indicative of the value of said input signal relative to said reference signal, said control register providing an update signal to said clock and logic means indicative of the logic state of said control register, output register means responsive to a digital signal from said clock and logic means for registering the binary logic state of said control register, decode logic means for decoding the binary number contained in said output register, memory means addressed by the output of said decode logic means with stored preselected numbers each having a length in excess of the length of said register means, the bit positions of said numbers being weighted to represent a certain voltage level, said memory means providing an output as a function of the number in said output register means, said memory output signal changing in value each time the contents of said output register means changes, voltage divider means comprising a reference voltage supply and switching means responsive to said memory output for providing said analog reference signal, transmitting means responsive to said clock and logic means for transmitting the digital output of said output register at preselected equal time intervals, and receiver means responsive to said digital output transmitted by said transmitting means for regenerating the first recited analog input signal.
Claim 2
Dependent Claim
311 words
A signal companding system providing a change in data compression simultaneously with data conversion comprising: means for comparing an input analog signal and a variable analog reference signal until said input signal and said reference signal are approximately equal and providing a digital comparator output signal indicative of the difference between said input analog signal and said variable analog reference signal, clock generator and successive approximation logic means responsive to said digital comparator output signal, control register means responsive to a digital signal from said clock generator and successive approximation logic means for temporarily storing binary numbers indicative of the value of said input signal relative to said reference signal, said control register providing an update signal to said clock and logic means indicative of the logic state of said control register, output register means responsive to a digital signal from said clock and logic means for registering the binary logic state of said control register, decode logic means for decoding the binary number contained in said output register, memory means addressed by the output of said decode logic means with stored preselected numbers each having a length in excess of the length of said register means, the bit positions of said numbers being weighted to represent a certain voltage level, said memory means providing an output as a function of the number in said output register means, said memory output signal changing in value each time the contents of said output register means changes, voltage divider means comprising a reference voltage supply and switching means responsive to said memory output for providing said analog reference signal, transmitting means responsive to said clock and logic means for transmitting the digital output of said output register at preselected equal time intervals, and receiver means responsive to said digital output transmitted by said transmitting means for regenerating the first recited analog input signal.
Claim 3
Dependent Claim
76 words
The system recited in claim 1 wherein said system receiver means further comprises: second logic means for processing the output of said output register, third register means responsive to said second logic means for receiving said processed output of said output register, second decode logic means for decoding the output of said third register means, and second memory means responsive to the decoded numbers in said third register means for regenerating the first recited input signal.
Claim 4
Dependent Claim
98 words
The system recited in claim 1 wherein said decode logic means includes means for addressing locations in said memory means, each decoded number from said output register representing an address location in said first memory, means responsive to the output from said first memory means for generating said reference signal according to the weighted voltage represented by the numbers at said addressed location, whereby although the output register is increased by said comparator means until said input signal and said reference signal are approximately equal, said referEnce signal is provided by said stored numbers in said first memory.
Claim 5
Dependent Claim
41 words
The system recited in claim 1 wherein said first memory means is a read-only memory, said input signal is an analog signal and said transmitted output of said output register is a digital signal representing the value of said input signal.
Claim 6
Dependent Claim
15 words
The system recited in claim 1 wherein said first memory means is a programmable memory.
Claim 7
Dependent Claim
110 words
The system recited in claim 1 further including counter means counted by clock pulses, and said first memory being addressed by the count in said counter means, said first memory storing preselected numbers for each number in said output register means, said stored numbers being relatively longer than the numbers in said output register means for increasing the comparison resolution of said system, said first memory means being responsive to the count in said counter means for providing an output each time the count equals one of the possible numbers in said output register means, said output from said first memory means controlling the generation of said variable reference signal.
Claim 8
Dependent Claim
54 words
The system recited in claim 6 further including second counter means responsive to the output of said first memory for generating said variable reference signal, fourth register means increasing in response to said comparator output and in response to said second counter means until said input signal and said reference signal are approximately equal.
Claim 9
Dependent Claim
49 words
The system recited in claim 7 further comprising a plurality of comparators and output register means, each comparator receiving independent input signals and said variable reference signal, each of said output register means providing an output when the respective input signal and the variable reference signal are approximately equal.
Claim 10
Dependent Claim
56 words
The system recited in claim 1 further comprising a plurality of comparators and output register means, each comparator receiving independent input signals and a common reference signal in response to the output from said first memory means, said output register means each providing an output signal when the input signals and reference signal are approximately equal.
Claim 11
Dependent Claim
22 words
The system recited in claim 1 wherein said input signal represents a voice signal and said system is a voice compander system.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-05-09 | 1975-11-08 | 1976-05-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-05-09 | 1979-11-08 | 1980-05-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-05-09 | 1983-11-08 | 1984-05-09 | $7700.00 | Window Closed / Lapsed |