US3662191A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Memory drive circuit
Assignee: GTE Sylvania Inc
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Filing: 1971-01-20
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Granted: 1972-05-09
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Expires: 1991-01-20
Abstract
Abstract Floating switch type of memory drive circuit having a transformer with the ends of the secondary winding connected to the base and emitter of a driving transistor. TTL NAND logic gates of the type having a pull-up transistor are connected to each end of the primary winding. When one of the gates is operated to produce a logic O at its output and the other gate is operated to produce a logic 1 at its output, the driving transistor turns on rapidly. When the operating states of the gates are subsequently reversed, the driving transistor turns off rapidly.
Inventors
- 👤 Albert H Aley
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 09:53
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/51; H03K17/56; H03K17/60; H03K17/601; G; G11; G11C; G11C11/00; G11C11/02; G11C11/06; G11C11/06007; H03K19/00; H03K19/0175; H03K19/018; H03K19/01825
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
571 words
A drive circuit including in combination a transformer having a primary winding and a secondary winding; a first circuit means including a first pair of transistors having the collector of one transistor and the emitter of the other transistor connected to one end of the primary winding, a first input means connected to the transistors of the first pair of transistors and operable to bias the one transistor in the conducting condition and the other transistor in the nonconducting condition during the occurrence of a first input condition at the input connection thereto, and operable to bias the one transistor in the non-conducting condition and the other transistor in the conducting condition during the occurrence of a second input condition at the input connection thereto; a second circuit means including a second pair of transistors having the collector of one transistor and the emitter of the other transistor connected to the other end of the primary winding, a second input means connected to the transistors of the second pair of transistors and operable to bias the one transistor in the conducting condition and the other transistor in the nonconducting condition during the occurrence of a first input condition at the input connection thereto, and operable to bias the one transistor in the non-conducting condition and the other transistor in the conducting condition during the occurrence of a second input condition at the input connection thereto; input data means connected to said first and second circuit means and operable to produce the first input condition at the input connection to the first input means and the second input condition at the input connection to the second input means in response to one set of inPut data being applied thereto, and operable to produce the first input condition at the input connection to the second input means and the second input condition at the input connection to the first input means in response to another set of input data being applied thereto; driving transistor circuit means including a driving transistor having its emitter connected to one end of the secondary winding of the transformer and its base connected to the other end of the secondary winding of the transformer, said driving transistor circuit means being operable to cause the driving transistor to conduct when a biasing voltage is present across the secondary winding of the transformer; whereby when the first input condition is applied at the input connection to the first input means and the second input condition is applied at the input connection to the second input means by the input data means, the one transistor of the first pair of transistors and the other transistor of the second pair of transistors conduct and current flows in one direction through the primary winding of the transformer inducing a forward biasing voltage across the secondary winding thereby causing the driving transistor to conduct; and subsequently when the first input condition is applied at the input connection to the second input means and the second input condition is applied at the input connection to the first input means by the input data means, the one transistor of the second pair of transistors and the other transistor of the first pair of transistors conduct and current flows in the opposite direction through the primary winding of the transformer inducing a reverse biasing voltage across the secondary winding thereby rapidly switching the driving transistor to non-conduction.
Claim 2
Dependent Claim
571 words
A drive circuit including in combination a transformer having a primary winding and a secondary winding; a first circuit means including a first pair of transistors having the collector of one transistor and the emitter of the other transistor connected to one end of the primary winding, a first input means connected to the transistors of the first pair of transistors and operable to bias the one transistor in the conducting condition and the other transistor in the nonconducting condition during the occurrence of a first input condition at the input connection thereto, and operable to bias the one transistor in the non-conducting condition and the other transistor in the conducting condition during the occurrence of a second input condition at the input connection thereto; a second circuit means including a second pair of transistors having the collector of one transistor and the emitter of the other transistor connected to the other end of the primary winding, a second input means connected to the transistors of the second pair of transistors and operable to bias the one transistor in the conducting condition and the other transistor in the nonconducting condition during the occurrence of a first input condition at the input connection thereto, and operable to bias the one transistor in the non-conducting condition and the other transistor in the conducting condition during the occurrence of a second input condition at the input connection thereto; input data means connected to said first and second circuit means and operable to produce the first input condition at the input connection to the first input means and the second input condition at the input connection to the second input means in response to one set of inPut data being applied thereto, and operable to produce the first input condition at the input connection to the second input means and the second input condition at the input connection to the first input means in response to another set of input data being applied thereto; driving transistor circuit means including a driving transistor having its emitter connected to one end of the secondary winding of the transformer and its base connected to the other end of the secondary winding of the transformer, said driving transistor circuit means being operable to cause the driving transistor to conduct when a biasing voltage is present across the secondary winding of the transformer; whereby when the first input condition is applied at the input connection to the first input means and the second input condition is applied at the input connection to the second input means by the input data means, the one transistor of the first pair of transistors and the other transistor of the second pair of transistors conduct and current flows in one direction through the primary winding of the transformer inducing a forward biasing voltage across the secondary winding thereby causing the driving transistor to conduct; and subsequently when the first input condition is applied at the input connection to the second input means and the second input condition is applied at the input connection to the first input means by the input data means, the one transistor of the second pair of transistors and the other transistor of the first pair of transistors conduct and current flows in the opposite direction through the primary winding of the transformer inducing a reverse biasing voltage across the secondary winding thereby rapidly switching the driving transistor to non-conduction.
Claim 3
Dependent Claim
282 words
A drive circuit in accordance with claim 1 wherein said first input means includes a first coupling transistor having its emitter connected to the base of the one transistor of the first pair of transistors and its collector connected to the base of the other transistor of the first pair and operable when in a conducting condition to bias the one transistor in the conducting condition and the other transistor in the non-conducting condition and operable when in a non-conducting condition to bias the one transistor in the non-conducting condition and the other transistor in the conducting condition, said first coupling transistor being biased to conduction during the occurrence of the first input condition at the input connection to the first input means and being biased to non-conduction during the occurrence of the second input condition at the input connection to the first input means; and said second input means includes a second coupling transistor having its emitter connected to the base of the one transistor of the second pair of transistors and its collector connected to the base of the other transistor of the second pair and operable when in a conducting condition to bias the one transistor in the conducting condition and the other transistor in the non-conducting condition and operable when in a non-conducting condition to bias the one transistor in the non-conducting condition and the other transistor in the conducting condition, said second coupling transistor being biased to conduction during the occurrence of the first input condition at the input connection to the second input means and being biased to non-conduction during the occurrence of the second input condition at the input connection to the second input means.
Claim 4
Dependent Claim
196 words
A drive circuit in accordance with claim 2 wherein said first input means includes a first input transistor having its emitter connected to a first input terminal, its collector connected to the base of the first coupling transistor, and its base connected through a resistance to a first source of reference potential; the collector of the first coupling transistor and the collector of the other transistor of the first pair of transistors are conneCted to the first source of reference potential; the emitter of the one transistor of the first pair of transistors is connected to a second source of reference potential; said second input means includes a second input transistor having its emitter connected to a second input terminal, its collector connected to the base of the second coupling transistor, and its base connected through a resistance to the first source of reference potential; the collector of the second coupling transistor and the collector of the other transistor of the second pair of transistors are connected to the first source of reference potential; and the emitter of the one transistor of the second pair of transistors is connected to the second source of reference potential.
Claim 5
Dependent Claim
50 words
A drive circuit in accordance with claim 3 wherein all of said transistors are of the same conductivity type; and the one end and the other end of the secondary winding of the transformer are in phase with the one end and the other end, respectively, of the primary winding.
Claim 6
Dependent Claim
276 words
Apparatus including in combination a first drive circuit in accordance with claim 1; a second drive circuit in accordance with claim 1; the collector of the driving transistor of the first drive circuit being connected to a third source of reference potential; the emitter of the driving transistor of the first drive circuit and the collector of the driving transistor of the second drive circuit being connected to an output terminal; the emitter of the driving transistor of the second drive circuit being connected to a fourth source of reference potential; whereby operation of the input data means of the first drive circuit to produce the first input condition at the input connection to the first input means and the second input condition at the input connection to the second input means of the first drive circuit and then to produce the first input condition at the input connection to the second input means and the second input condition at the input connection to the first input means of the first drive circuit produces a pulse of one polarity at the output terminal, and operation of the input data means of the second drive circuit to produce the first input condition at the input connection to the first input means and the second input condition at the input connection to the second input means of the second drive circuit and then to produce the first input condition at the input connection to the second input means and the second input condition at the input connection to the first input means of the second drive circuit produces a pulse of the opposite polarity at the output terminal.
Claim 7
Dependent Claim
414 words
Apparatus including in combination a first drive circuit in accordance with claim 3; a second drive circuit in accordance with claim 3; the collector of the driving transistor of the first drive circuit being connected to a third source of reference potential; the emitter of the driving transistor of the first drive circuit and the collector of the driving transistor of the second drive circuit being connected to an output terminal; the emitter of the driving transistor of the second drive circuit being connected to a fourth source of reference potential of opposite polarity from said third source; the input data means of the first drive circuit and the input data means of the second drive circuit having common input data connections, the first input condition being produced at the input connection to the first input means and the second input condition being produced at the input connection to the second input means of the first drive circuit when a first set of input data is present at the common input data connections, the first input condition being produced at the input connection to the second input means and the second input condition being produced at the input connection to the first input means of the first drive circuit when a second set of input data is present at the common input data connections, the first input condition being produced at the input connection to the first input means and the second input condition being produced at the input connection to the second input means of the second drive circuit when a third set of input data is present at the common input data connections and the first input condition being produced at the input connection to the second input means and the second input condition being produced at the input connection to the first input means of the second drive circuit when a fourth set of input data is present at the common input data connections; whereby the presence of the first set of input data at the common input data connections and then the presence of the second set of input data at the common input data connections produces a pulse of one polarity at the output terminal, and the presence of the third set of input data at the common input data connections and then the presence of the fourth set of input data at the common input data connections produces a pulse of the opposite polarity at the output terminal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-05-09 | 1975-11-08 | 1976-05-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-05-09 | 1979-11-08 | 1980-05-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-05-09 | 1983-11-08 | 1984-05-09 | $7700.00 | Window Closed / Lapsed |