Abstract This application discloses a storage cell which employs a single gated multi-emitter semiconductor device that exhibits a negative resistance operating characteristic. The semiconductor device is biased to have two stable operating states on this negative resistance characteristic and is addressed by a word line connected to one of its emitters and a bit line connected to the other of its emitters. A parasitic transistor is formed by the two emitters and the gating layer of the semiconductor device. By application of half-select pulses to the word and bit lines, the parasitic transistor is broken down to cause a temporary current flow in the gating region of the semiconductor device. While this current flows in the gating region, the operating characteristic of the semiconductor device is changed so that there is only one stable operating state for the semiconductor device. The operation of the semiconductor device therefore shifts to this single operating state. When the temporary current flow ends the semiconductor device will be in a low voltage, high current stable state along the negative resistance characteristic irrespective of the operating state of the semiconductor device prior to the application of the half select pulses. When such a storage cell is manufactured in monolithic form, very high cell densities and extremely high operating speeds are obtainable.
In a memory with storage cells addressed by word and bit lines, the improvement comprising a new storage cell including: a multi-emitter gated semiconductor device exhibiting an operating characteristic changeable by the application of current to the gating region of the device and having emitter regions in the gating region so that the emitter regions with the gating region form a transistor, one of said emitter regions being coupled to a word line and another emitter region being coupled to a bit line; load means for biasing said semiconductor device so that the semiconductor device operates along a negative resistance operating characteristic of said device and has two stable operating states along said negative resistance operating characteristic, the first state a high voltage low current state and the second state a low voltage high current state; bias means for coupling the base of said multi-emitter gated semiconductor device to the emitters of said semiconductor device so as to bias the semiconductor device to operate on said negative resistance characteristic, and; means for application of half-select pulses to both the word line and bit line which upon simultaneous application to the emitters of said semiconductor devices causes conduction of said transistor from emitter-to-emitter to inject current into the gating region of the semiconductor device to temporarily change the operation of said semiconductor device from said negative resistance characteristic to a second operating characteristic so that the semiconductor device is switched from the first stable state to the second stable state when operation of the semiconductor device returns to operation along said negative resistance operating characteristic at the end of the half-select pulses.
Claim 2
Dependent Claim
271 words
In a memory with storage cells addressed by word and bit lines, the improvement comprising a new storage cell including: a multi-emitter gated semiconductor device exhibiting an operating characteristic changeable by the application of current to the gating region of the device and having emitter regions in the gating region so that the emitter regions with the gating region form a transistor, one of said emitter regions being coupled to a word line and another emitter region being coupled to a bit line; load means for biasing said semiconductor device so that the semiconductor device operates along a negative resistance operating characteristic of said device and has two stable operating states along said negative resistance operating characteristic, the first state a high voltage low current state and the second state a low voltage high current state; bias means for coupling the base of said multi-emitter gated semiconductor device to the emitters of said semiconductor device so as to bias the semiconductor device to operate on said negative resistance characteristic, and; means for application of half-select pulses to both the word line and bit line which upon simultaneous application to the emitters of said semiconductor devices causes conduction of said transistor from emitter-to-emitter to inject current into the gating region of the semiconductor device to temporarily change the operation of said semiconductor device from said negative resistance characteristic to a second operating characteristic so that the semiconductor device is switched from the first stable state to the second stable state when operation of the semiconductor device returns to operation along said negative resistance operating characteristic at the end of the half-select pulses.
Claim 3
Dependent Claim
15 words
The storage cell of claim 1 wherein said multi-emitter semiconductor device is a multi-emitter transistor.
Claim 4
Dependent Claim
25 words
The storage cell of claim 2 wherein said bias means is a unidirectional current path means for discharging the base-collector junction of the multi-emitter transistOr.
Claim 5
Dependent Claim
39 words
The storage cell of claim 3 said unidirectional current path means comprises two diodes coupled back to back between said emitters and resistor coupling the common terminals of the back to back diodes to the base of the transistor.