Circuit arrangement for converting signal voltages

Claim 1

A logic signal level converter circuit for conducting the output of a saturated type logic circuit to the input of an unsaturated type logic circuit comprising a first rectifying junction, an input terminal connected to said first rectifying junction, a first voltage supply terminal, a first resistor connecting said first rectifying junction to said first voltage supply terminal, a second rectifying junction connected to said first voltage supply terminal via said first resistor, an emitter follower transistor circuit including a base electrode connected to said first voltage supply terminal via said second rectifying junction and said first resistor, a collector electrode, a second resistor connecting said collector electrode to said first voltage supply terminal, an emitter electrode, and a multiemitter transistor including base and collector electrodes connected to said emitter electrode of said emitter follower transistor circuit, a first emitter of said multi-emitter transistor connected to a fixed potential to fix the output signals of said converter circuit to a predetermined level, a second voltage supply terminal poled opposite said first voltage supply terminal, a second emitter of said multi-emitter transistor, and a voltage divider connected between said second emitter and said second voltage supply terminal and including a junction point serving as an output terminal.