Checking by pseudoduplication

Claim 1

An apparatus for detecting errors comprising the combination of: a first and second data register for storing representations of binary data; an arithmetic-logical unit capable of performing the functions of addition, subtraction, AND, OR, EXCLUSIVE OR, and shift, said arithmetic-logical unit having at least as many data paths as there are data bits in said first and second data registers, each data path having an output, said arithmetic-logical unit having paired inputs for each data bit position in said first and second data register; a first gating means active in a first mode to gate the data bits in said first and second data registers to said paired inputs of said arithmetic-logical unit and active during a second mode to gate the data from said first and second data registers to a different set of paired inputs than the set of paired inputs employed during said first mode; a third data register; a second gating means active in said first mode to gate data from the outputs of said arithmetic-logical unit to said third data register and active during said second mode to produce a gating output, said gating output being equal to the output of said arithmetic-logical unit during said second mode; and a comparison means for comparing the contents of said third data register and said gating output, said comparison means producing an error signal when any data bit in said third data register is different from the properly aligned gating output.

Claim 2

An apparatus for detecting errors comprising the combination of: a first and second data register for storing representations of binary data; an arithmetic-logical unit capable of performing the functions of addition, subtraction, AND, OR, EXCLUSIVE OR, and shift, said arithmetic-logical unit having at least as many data paths as there are data bits in said first and second data registers, each data path having an output, said arithmetic-logical unit having paired inputs for each data bit position in said first and second data register; a first gating means active in a first mode to gate the data bits in said first and second data registers to said paired inputs of said arithmetic-logical unit and active during a second mode to gate the data from said first and second data registers to a different set of paired inputs than the set of paired inputs employed during said first mode; a third data register; a second gating means active in said first mode to gate data from the outputs of said arithmetic-logical unit to said third data register and active during said second mode to produce a gating output, said gating output being equal to the output of said arithmetic-logical unit during said second mode; and a comparison means for comparing the contents of said third data register and said gating output, said comparison means producing an error signal when any data bit in said third data register is different from the properly aligned gating output.

Claim 4

A method of detecting errors in computer calculations comprising the steps of: performing a first calculation to produce a first result using a first set of data paths in the calculational circuitry; storing said first result; performing a second calculation identical to said first calculation to produce a second result, said second calculation using a second set of data paths different from said first set of data paths, at least one of said second set of data paths being the same as used during said first calculation for a different pair of data bits; and comparing said second result with said first result to determine whether said first result is identical to said second result.

Claim 5

A method of detecting errors in computer calculations comprising the steps of: performing a first calculation to produce a first result using a first set of data paths in the calculational circuitry; storing said first result; performing a second calculation identical to said first calculation to produce a second result, said second calculation using a second set of data paths different from said first set of data paths, at least one of said second set of data paths being the same as used during said first calculation for a different pair of data bits; and comparing said second result with said first result to determine whether said first result is identical to said second result.

Claim 7

An apparatus for detecting computational errors in a computational unit comprising: a first and second data register each for storing binary data and having a plurality of bit positions in each of said first and second data registers; an arithmetic-logical unit having a plurality of data paths therethrough, each data path having an output, a first and second entry point and each said data path being capable of performing addition, subtraction, OR, AND, EXCLUSIVE OR, and shift operations upon the data entering said first and second entry points, said arithmetic-logical unit having more than as many data paths as there are binary bit positions in either of said first or second data registers; a plurality of first gating means, each of said first gating means active during said first phase of operation to gate binary data from said first data register to at least some of said first input points; a plUrality of second gating means, each of said second gating means active during said first phase of operation to gate binary data from said second data register to at least some of said second input points, said activated second input points being in the same data paths as the first input points activated by said plurality of first gating means; a third data register for storing binary data; a plurality of third gating means for gating the output of said arithmetic-logical unit to said third data register during said first phase of operation; a plurality of fourth gating means, each of said fourth gating means active during a second phase of operation to gate the binary data from said first data register to at least some of said first input points, each activated input point during said second phase of operation being a different first input point than was activated by said first gating means during said first phase of operation for each binary bit position in said first data register; a plurality of fifth gating means, each of said fifth gating means active during a second phase of operation to gate the binary data from said second data register to at least some of said second input points, said activated second input points being in the same data paths as the first input points activated by said plurality of fourth gating means; and a comparison means for comparing the contents of said third data register and the output of said arithmetic-logical unit during said second phase of operation, said comparison means producing an error signal when any data bit in said third data register is different from the properly associated output bit generated by said arithmetic-logical unit during said second phase of operation.

Claim 8

An apparatus for detecting computational errors in a computational unit comprising: a first and second data register each for storing binary data and having a plurality of bit positions in each of said first and second data registers; an arithmetic-logical unit having a plurality of data paths therethrough, each data path having an output, a first and second entry point and each said data path being capable of performing addition, subtraction, OR, AND, EXCLUSIVE OR, and shift operations upon the data entering said first and second entry points, said arithmetic-logical unit having more than as many data paths as there are binary bit positions in either of said first or second data registers; a plurality of first gating means, each of said first gating means active during said first phase of operation to gate binary data from said first data register to at least some of said first input points; a plUrality of second gating means, each of said second gating means active during said first phase of operation to gate binary data from said second data register to at least some of said second input points, said activated second input points being in the same data paths as the first input points activated by said plurality of first gating means; a third data register for storing binary data; a plurality of third gating means for gating the output of said arithmetic-logical unit to said third data register during said first phase of operation; a plurality of fourth gating means, each of said fourth gating means active during a second phase of operation to gate the binary data from said first data register to at least some of said first input points, each activated input point during said second phase of operation being a different first input point than was activated by said first gating means during said first phase of operation for each binary bit position in said first data register; a plurality of fifth gating means, each of said fifth gating means active during a second phase of operation to gate the binary data from said second data register to at least some of said second input points, said activated second input points being in the same data paths as the first input points activated by said plurality of fourth gating means; and a comparison means for comparing the contents of said third data register and the output of said arithmetic-logical unit during said second phase of operation, said comparison means producing an error signal when any data bit in said third data register is different from the properly associated output bit generated by said arithmetic-logical unit during said second phase of operation.

Claim 9

An apparatus for detecting computational errors in a computational unit comprising: a first and second data register each for storing binary data and having a plurality of bit positions in each of said first and second data register; an arithmetic-logical unit having a plurality of data paths therethrough, each data path having an output, the first and second entry point and each said data path being capable of performing OR, AND, and EXCLUSIVE OR operations upon the data entering said first and second entry points, said arithmetic-logical unit having at least as many data paths as there are binary bit positions in either of said first or second data registers; a plurality of first gating means, each of said first gating means active during a first phase of operation to gate binary data from said first data register to at least some of said first input points; a plurality of second gating means, each of said second gating means active during said first phase of operation to gate binary data from said second data register to at least some of said second input points, said activated second input points being in the same data paths as the first input points activated by said plurality of first gating means; a third data register for storing binary data; a plurality of third gating means for gating the output of said arithmetic-logical unit to said third data register during said first phase of operation; a plurality of fourth gating means, each of said fourth gating means active during a second phase of operation to gate the binary data from said first data register to at least some of said first input points, each activated input point during said second phase of operation being a different first input point than was activated by said first gating means during said first phase of operation for each binary bit position in said first data register; a plurality of fifth gating means, each of said fifth gating means active during a second phase of operation to gate the binary data from said second data register to at least some of said second input points, said activated second input points being in the same data paths as the first input points activated by said plurality of fourth gating means; aNd a comparison means for comparing the contents of said third data register and the output of said arithmetic-logical unit during said second phase of operation, said comparison means producing an error signal when any data bit in said third register is different from the properly associated output bit generated by said arithmetic-logical unit during said second phase of operation.

Claim 10

An apparatus for detecting computational errors in a computational unit comprising: a first and second data register each for storing binary data and having a plurality of bit positions in each of said first and second data register; an arithmetic-logical unit having a plurality of data paths therethrough, each data path having an output, the first and second entry point and each said data path being capable of performing OR, AND, and EXCLUSIVE OR operations upon the data entering said first and second entry points, said arithmetic-logical unit having at least as many data paths as there are binary bit positions in either of said first or second data registers; a plurality of first gating means, each of said first gating means active during a first phase of operation to gate binary data from said first data register to at least some of said first input points; a plurality of second gating means, each of said second gating means active during said first phase of operation to gate binary data from said second data register to at least some of said second input points, said activated second input points being in the same data paths as the first input points activated by said plurality of first gating means; a third data register for storing binary data; a plurality of third gating means for gating the output of said arithmetic-logical unit to said third data register during said first phase of operation; a plurality of fourth gating means, each of said fourth gating means active during a second phase of operation to gate the binary data from said first data register to at least some of said first input points, each activated input point during said second phase of operation being a different first input point than was activated by said first gating means during said first phase of operation for each binary bit position in said first data register; a plurality of fifth gating means, each of said fifth gating means active during a second phase of operation to gate the binary data from said second data register to at least some of said second input points, said activated second input points being in the same data paths as the first input points activated by said plurality of fourth gating means; aNd a comparison means for comparing the contents of said third data register and the output of said arithmetic-logical unit during said second phase of operation, said comparison means producing an error signal when any data bit in said third register is different from the properly associated output bit generated by said arithmetic-logical unit during said second phase of operation.